TimeQuest Timing Analyzer report for atari800core
Wed Sep 11 22:04:46 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'FPGA_CLK'
 27. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'FPGA_CLK'
 31. Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Output Enable Times
 47. Minimum Output Enable Times
 48. Output Disable Times
 49. Minimum Output Disable Times
 50. Slow 1200mV 85C Model Metastability Report
 51. Slow 1200mV 0C Model Fmax Summary
 52. Slow 1200mV 0C Model Setup Summary
 53. Slow 1200mV 0C Model Hold Summary
 54. Slow 1200mV 0C Model Recovery Summary
 55. Slow 1200mV 0C Model Removal Summary
 56. Slow 1200mV 0C Model Minimum Pulse Width Summary
 57. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 58. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 59. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 61. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 65. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 69. Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Recovery: 'FPGA_CLK'
 71. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 72. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 74. Slow 1200mV 0C Model Removal: 'FPGA_CLK'
 75. Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 78. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 80. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 81. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 86. Setup Times
 87. Hold Times
 88. Clock to Output Times
 89. Minimum Clock to Output Times
 90. Output Enable Times
 91. Minimum Output Enable Times
 92. Output Disable Times
 93. Minimum Output Disable Times
 94. Slow 1200mV 0C Model Metastability Report
 95. Fast 1200mV 0C Model Setup Summary
 96. Fast 1200mV 0C Model Hold Summary
 97. Fast 1200mV 0C Model Recovery Summary
 98. Fast 1200mV 0C Model Removal Summary
 99. Fast 1200mV 0C Model Minimum Pulse Width Summary
100. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
103. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
104. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
106. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
108. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
109. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
110. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
111. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
112. Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
113. Fast 1200mV 0C Model Recovery: 'FPGA_CLK'
114. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
115. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
116. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
117. Fast 1200mV 0C Model Removal: 'FPGA_CLK'
118. Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
119. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
120. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
121. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
122. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
123. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
124. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
125. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
126. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
127. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
129. Setup Times
130. Hold Times
131. Clock to Output Times
132. Minimum Clock to Output Times
133. Output Enable Times
134. Minimum Output Enable Times
135. Output Disable Times
136. Minimum Output Disable Times
137. Fast 1200mV 0C Model Metastability Report
138. Multicorner Timing Analysis Summary
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Board Trace Model Assignments
144. Input Transition Times
145. Signal Integrity Metrics (Slow 1200mv 0c Model)
146. Signal Integrity Metrics (Slow 1200mv 85c Model)
147. Signal Integrity Metrics (Fast 1200mv 0c Model)
148. Setup Transfers
149. Hold Transfers
150. Recovery Transfers
151. Removal Transfers
152. Report TCCS
153. Report RSKM
154. Unconstrained Paths
155. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone IV E                                                      ;
; Device Name        ; EP4CE15E22C7                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Wed Sep 11 22:04:38 2019 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Clock Name                                                                          ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                             ; Source                                                                                ; Targets                                                                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                            ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                    ;                                                                                       ; { FPGA_CLK }                                                                            ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                 ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 36.23 MHz  ; 36.23 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 98.22 MHz  ; 98.22 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 100.7 MHz  ; 100.7 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 144.09 MHz ; 144.09 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 211.33 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                          ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.696 ; -274.155      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675 ; -1.675        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.292 ; -11.281       ;
; FPGA_CLK                                                                            ; 0.163  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.269  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.870  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.745 ; -130.071      ;
; FPGA_CLK                                                                            ; -0.769 ; -0.769        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.341  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.413  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.413  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.635 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                       ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.397 ; -21.573       ;
; FPGA_CLK                                                                            ; -0.150 ; -3.900        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.633  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.012  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.124 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.500 ; -12.925       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.351  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.830  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.215  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.530  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.596  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.720  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.535  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.374  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.260 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.594 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.530 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.425     ; 1.240      ;
; -3.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.425     ; 1.206      ;
; -3.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.425     ; 1.070      ;
; -3.439 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.994      ;
; -3.417 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.972      ;
; -3.415 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.414     ; 0.970      ;
; -3.258 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.438     ; 0.789      ;
; -3.257 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.438     ; 0.788      ;
; -3.257 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.437     ; 0.789      ;
; -3.253 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 1.161      ;
; -3.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.427     ; 0.790      ;
; -3.227 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 1.135      ;
; -3.214 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 1.134      ;
; -3.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 1.150      ;
; -3.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 1.137      ;
; -3.088 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.996      ;
; -3.087 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.995      ;
; -3.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.995      ;
; -3.072 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.992      ;
; -3.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.968      ;
; -3.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.978      ;
; -3.057 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.976      ;
; -3.056 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.976      ;
; -3.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.975      ;
; -3.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.963      ;
; -3.051 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.971      ;
; -3.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.969      ;
; -3.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.035     ; 0.979      ;
; -3.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.035     ; 0.977      ;
; -3.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 1.015      ;
; -3.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.020     ; 0.988      ;
; -3.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.035     ; 0.971      ;
; -3.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.035     ; 0.969      ;
; -3.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.986     ; 1.015      ;
; -3.025 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 1.000      ;
; -3.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.020     ; 0.968      ;
; -3.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.034     ; 0.953      ;
; -3.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 1.004      ;
; -3.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 0.993      ;
; -3.015 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.034     ; 0.950      ;
; -3.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.987      ;
; -3.013 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.986     ; 0.996      ;
; -3.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.034     ; 0.935      ;
; -2.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 0.973      ;
; -2.997 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.996     ; 0.970      ;
; -2.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 0.969      ;
; -2.993 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.983     ; 0.979      ;
; -2.992 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.977      ;
; -2.991 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.976      ;
; -2.990 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 0.965      ;
; -2.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.982     ; 0.955      ;
; -2.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.969     ; 0.953      ;
; -2.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.837      ;
; -2.916 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.835      ;
; -2.908 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.064     ; 0.813      ;
; -2.908 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.064     ; 0.813      ;
; -2.906 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.826      ;
; -2.905 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.813      ;
; -2.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.054     ; 0.812      ;
; -2.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.054     ; 0.812      ;
; -2.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.816      ;
; -2.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.051     ; 0.814      ;
; -2.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.051     ; 0.813      ;
; -2.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.814      ;
; -2.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.813      ;
; -2.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.813      ;
; -2.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.812      ;
; -2.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.050     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.813      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.049     ; 0.812      ;
; -2.892 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.048     ; 0.813      ;
; -2.882 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.062     ; 0.789      ;
; -2.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.061     ; 0.789      ;
; -2.862 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.836      ;
; -2.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.835      ;
; -2.850 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.835      ;
; -2.842 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.023     ; 0.788      ;
; -2.840 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.814      ;
; -2.839 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.813      ;
; -2.838 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.812      ;
; -2.838 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.995     ; 0.812      ;
; -2.834 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.015     ; 0.788      ;
; -2.830 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.815      ;
; -2.819 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.999     ; 0.789      ;
; -2.813 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.994     ; 0.788      ;
; -2.808 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.793      ;
; -2.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.790      ;
; -2.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.790      ;
; -2.804 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.984     ; 0.789      ;
; 2.937  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.557      ;
; 3.003  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 8.502      ;
; 3.103  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 8.403      ;
; 3.110  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 8.395      ;
; 3.137  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 8.369      ;
; 3.142  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 8.364      ;
; 3.246  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 8.260      ;
; 3.256  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 8.250      ;
; 3.279  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 8.217      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.675 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.758     ; 1.164      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.292 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.431      ;
; -0.261 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.400      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.358      ;
; -0.242 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.381      ;
; -0.241 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.357      ;
; -0.217 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.332      ;
; -0.215 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.330      ;
; -0.213 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.328      ;
; -0.205 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.320      ;
; -0.197 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.324      ;
; -0.192 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.307      ;
; -0.192 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.319      ;
; -0.190 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.317      ;
; -0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.314      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.299      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.311      ;
; -0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.310      ;
; -0.182 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.309      ;
; -0.182 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.310      ;
; -0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.295      ;
; -0.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.307      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.306      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.317      ;
; -0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.304      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.300      ;
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.310      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.296      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.296      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.309      ;
; -0.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.309      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.295      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.308      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.296      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.296      ;
; -0.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.307      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.306      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.304      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.292      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.304      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.301      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.289      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.302      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.289      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.301      ;
; -0.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.299      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.297      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.285      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.296      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.293      ;
; -0.151 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.278      ;
; -0.150 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.289      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.287      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.285      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.286      ;
; -0.143 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.283      ;
; -0.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.278      ;
; -0.134 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.273      ;
; -0.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.261      ;
; -0.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.249      ;
; -0.084 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.200      ;
; -0.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 1.192      ;
; -0.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.191      ;
; -0.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.177      ;
; -0.059 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.175      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.168      ;
; -0.051 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.218      ; 1.166      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.164      ;
; -0.046 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.231      ; 1.174      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.184      ;
; -0.040 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.156      ;
; -0.037 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.176      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.152      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.151      ;
; -0.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.174      ;
; -0.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.147      ;
; -0.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.219      ; 1.136      ;
; -0.016 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.155      ;
; -0.007 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.230      ; 1.134      ;
; -0.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.146      ;
; -0.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.243      ; 1.144      ;
; 0.041  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.242      ; 1.098      ;
; 5.326  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.734     ; 6.548      ;
; 5.461  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.718     ; 6.429      ;
; 6.424  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.809      ;
; 6.543  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.690      ;
; 6.854  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.363     ; 5.391      ;
; 6.868  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.365      ;
; 6.909  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.324      ;
; 7.016  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.363     ; 5.229      ;
; 7.026  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.207      ;
; 7.079  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.154      ;
; 7.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 5.135      ;
; 7.135  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.098      ;
; 7.144  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.089      ;
; 7.196  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 5.037      ;
; 7.266  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.375     ; 4.967      ;
; 7.278  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 4.973      ;
; 7.313  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.357     ; 4.938      ;
; 7.374  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.643      ; 6.684      ;
; 7.376  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.363     ; 4.869      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.163   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.273      ; 3.874      ;
; 195.268 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.304     ; 1.627      ;
; 195.541 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.195      ; 4.652      ;
; 196.706 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.195      ;
; 196.725 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.176      ;
; 196.833 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.068      ;
; 196.838 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.063      ;
; 196.839 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.062      ;
; 196.857 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.044      ;
; 196.858 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 3.043      ;
; 196.924 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.977      ;
; 196.961 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.940      ;
; 196.965 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.936      ;
; 196.970 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.931      ;
; 196.970 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.931      ;
; 196.971 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.930      ;
; 196.989 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.912      ;
; 196.989 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.912      ;
; 196.990 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.911      ;
; 197.056 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.845      ;
; 197.058 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.843      ;
; 197.090 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.811      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.808      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.808      ;
; 197.097 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.804      ;
; 197.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.799      ;
; 197.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.799      ;
; 197.103 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.798      ;
; 197.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.792      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.780      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.780      ;
; 197.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.779      ;
; 197.188 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.713      ;
; 197.190 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.711      ;
; 197.191 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.710      ;
; 197.222 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.679      ;
; 197.225 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.676      ;
; 197.225 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.676      ;
; 197.229 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.672      ;
; 197.230 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.671      ;
; 197.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.667      ;
; 197.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.667      ;
; 197.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.666      ;
; 197.236 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.665      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.660      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.648      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.648      ;
; 197.254 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.647      ;
; 197.255 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.646      ;
; 197.320 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.581      ;
; 197.320 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.581      ;
; 197.322 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.579      ;
; 197.323 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.578      ;
; 197.354 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.547      ;
; 197.357 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.544      ;
; 197.357 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.544      ;
; 197.361 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.540      ;
; 197.362 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.539      ;
; 197.363 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.538      ;
; 197.366 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.535      ;
; 197.366 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.535      ;
; 197.367 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.534      ;
; 197.367 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.534      ;
; 197.368 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.533      ;
; 197.373 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.528      ;
; 197.385 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.516      ;
; 197.385 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.516      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.515      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.515      ;
; 197.387 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.514      ;
; 197.452 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.449      ;
; 197.452 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.449      ;
; 197.453 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.448      ;
; 197.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.447      ;
; 197.455 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.446      ;
; 197.486 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.415      ;
; 197.489 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.412      ;
; 197.489 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.412      ;
; 197.493 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.408      ;
; 197.494 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.407      ;
; 197.495 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.406      ;
; 197.496 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.405      ;
; 197.498 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.403      ;
; 197.499 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.402      ;
; 197.499 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.402      ;
; 197.500 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.401      ;
; 197.505 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.396      ;
; 197.517 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.384      ;
; 197.517 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.384      ;
; 197.518 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.383      ;
; 197.518 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.383      ;
; 197.519 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.382      ;
; 197.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.402      ;
; 197.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.403      ;
; 197.545 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.383      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.317      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.317      ;
; 197.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.317      ;
; 197.585 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.316      ;
; 197.586 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.097     ; 2.315      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.269 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 4.236      ;
; 1.389 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.109      ;
; 1.396 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 4.109      ;
; 1.489 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 4.007      ;
; 1.736 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.759      ;
; 1.736 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.759      ;
; 1.792 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.704      ;
; 1.812 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.684      ;
; 1.868 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.627      ;
; 1.868 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.627      ;
; 1.890 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 3.603      ;
; 1.919 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.172     ; 3.575      ;
; 1.919 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.577      ;
; 1.939 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.557      ;
; 2.046 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.172     ; 3.448      ;
; 2.072 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.436      ;
; 2.083 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.417      ;
; 2.088 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.410      ;
; 2.089 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.410      ;
; 2.097 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.184     ; 3.385      ;
; 2.118 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.390      ;
; 2.118 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.390      ;
; 2.127 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.373      ;
; 2.187 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.320      ;
; 2.215 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.281      ;
; 2.229 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 3.282      ;
; 2.245 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.263      ;
; 2.245 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.263      ;
; 2.319 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.188      ;
; 2.322 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.169     ; 3.175      ;
; 2.407 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 3.086      ;
; 2.407 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 3.086      ;
; 2.492 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.122      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.497 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.118      ;
; 2.504 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 2.991      ;
; 2.509 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.105      ;
; 2.511 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.103      ;
; 2.513 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.101      ;
; 2.527 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.154     ; 2.985      ;
; 2.533 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.082      ;
; 2.534 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 2.959      ;
; 2.534 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.173     ; 2.959      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.548 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.065      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.551 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 3.064      ;
; 2.563 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.051      ;
; 2.564 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.050      ;
; 2.564 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.050      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.596 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 3.017      ;
; 2.608 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.006      ;
; 2.609 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.005      ;
; 2.611 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 3.003      ;
; 2.614 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.002      ;
; 2.615 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 3.001      ;
; 2.637 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.861      ;
; 2.653 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.963      ;
; 2.657 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.959      ;
; 2.659 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.957      ;
; 2.689 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 2.820      ;
; 2.696 ; SDRAM_ADDR[11]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 2.813      ;
; 2.700 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 2.805      ;
; 2.731 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.757     ; 1.165      ;
; 2.811 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 2.698      ;
; 2.828 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 2.677      ;
; 2.828 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 2.677      ;
; 2.840 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.773      ;
; 2.842 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.771      ;
; 2.844 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 2.770      ;
; 2.850 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.144     ; 2.787      ;
; 2.861 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 2.753      ;
; 2.864 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.749      ;
; 2.865 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.748      ;
; 2.926 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.690      ;
; 2.927 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.165     ; 2.689      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.870  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.480     ;
; 1.889  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.461     ;
; 2.002  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.348     ;
; 2.021  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.329     ;
; 2.060  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.290     ;
; 2.061  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.289     ;
; 2.079  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.271     ;
; 2.080  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.270     ;
; 2.100  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.250     ;
; 2.119  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.231     ;
; 2.177  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.173     ;
; 2.192  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.158     ;
; 2.193  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.157     ;
; 2.196  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.154     ;
; 2.211  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.139     ;
; 2.212  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.138     ;
; 2.232  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.118     ;
; 2.251  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.099     ;
; 2.309  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.041     ;
; 2.328  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 15.022     ;
; 2.598  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.752     ;
; 2.744  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 14.605     ;
; 2.763  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 14.586     ;
; 2.788  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.562     ;
; 2.789  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.561     ;
; 2.828  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.522     ;
; 2.876  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 14.473     ;
; 2.895  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 14.454     ;
; 2.905  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.445     ;
; 3.042  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.308     ;
; 3.232  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.118     ;
; 3.233  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.117     ;
; 3.272  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.078     ;
; 3.349  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 14.001     ;
; 3.472  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 13.877     ;
; 3.640  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 13.710     ;
; 3.830  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 13.520     ;
; 3.831  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 13.519     ;
; 3.870  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 13.480     ;
; 3.916  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 13.433     ;
; 3.947  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 13.403     ;
; 4.514  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 12.835     ;
; 4.569  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 12.786     ;
; 4.588  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 12.767     ;
; 4.701  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 12.654     ;
; 4.720  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 12.635     ;
; 4.937  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 12.413     ;
; 5.127  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 12.223     ;
; 5.128  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 12.222     ;
; 5.167  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 12.183     ;
; 5.244  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 12.106     ;
; 5.297  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 12.058     ;
; 5.442  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.757     ; 1.391      ;
; 5.741  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 11.614     ;
; 5.811  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 11.538     ;
; 6.339  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 11.016     ;
; 7.636  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 9.719      ;
; 7.691  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.768      ;
; 7.705  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.754      ;
; 7.776  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.683      ;
; 7.795  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.664      ;
; 7.814  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.642      ;
; 7.826  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.633      ;
; 7.827  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.632      ;
; 7.833  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.623      ;
; 7.837  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.622      ;
; 7.841  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.618      ;
; 7.908  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.551      ;
; 7.927  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.532      ;
; 7.946  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.510      ;
; 7.962  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.497      ;
; 7.965  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.491      ;
; 7.973  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.486      ;
; 8.165  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.291      ;
; 8.184  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.272      ;
; 8.297  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.159      ;
; 8.316  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 9.140      ;
; 8.433  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 9.026      ;
; 8.504  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.955      ;
; 8.542  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.914      ;
; 8.569  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.890      ;
; 8.843  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.616      ;
; 8.893  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.563      ;
; 8.948  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.511      ;
; 8.979  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.480      ;
; 8.986  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.470      ;
; 9.337  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 8.119      ;
; 9.441  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 8.018      ;
; 9.546  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 7.913      ;
; 9.577  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 7.882      ;
; 9.584  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.872      ;
; 9.935  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 7.521      ;
; 10.738 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 6.721      ;
; 10.843 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 6.616      ;
; 10.874 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.070     ; 6.585      ;
; 10.881 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.575      ;
; 11.232 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.073     ; 6.224      ;
; 11.561 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.182     ; 5.786      ;
; 11.664 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.182     ; 5.683      ;
; 11.719 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.174     ; 5.636      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 0.987      ;
; -1.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.020      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.043      ;
; -1.689 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.043      ;
; -1.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 1.022      ;
; -1.686 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.023      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.026      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.049      ;
; -1.679 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.030      ;
; -1.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.043      ;
; -1.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.055      ;
; -1.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 1.036      ;
; -1.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.061      ;
; -1.669 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.063      ;
; -1.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.043      ;
; -1.665 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.044      ;
; -1.664 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.068      ;
; -1.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.080      ;
; -1.651 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.080      ;
; -1.651 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.081      ;
; -1.648 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.061      ;
; -1.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.076      ;
; -1.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.065      ;
; -1.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.088      ;
; -1.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.066      ;
; -1.641 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.081      ;
; -1.640 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.081      ;
; -1.639 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.083      ;
; -1.639 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.414      ; 1.069      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.083      ;
; -1.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.084      ;
; -1.637 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.095      ;
; -1.635 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.086      ;
; -1.634 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.098      ;
; -1.630 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.079      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.080      ;
; -1.629 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.080      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.095      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.083      ;
; -1.626 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.095      ;
; -1.625 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.084      ;
; -1.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.120      ;
; -1.611 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.121      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.124      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.124      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.103      ;
; -1.604 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.127      ;
; -1.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.119      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.121      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.135      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.135      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.124      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.137      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.138      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.138      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.137      ;
; -1.593 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.139      ;
; -1.593 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.128      ;
; -1.592 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.139      ;
; -1.589 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.437      ; 1.142      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.144      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.144      ;
; -1.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.137      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.140      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.140      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.140      ;
; -1.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.426      ; 1.141      ;
; -1.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.152      ;
; -1.548 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.427      ; 1.173      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.202      ;
; -1.507 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.215      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.220      ;
; -1.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.428      ; 1.222      ;
; -1.488 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.221      ;
; -1.481 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.228      ;
; -1.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.231      ;
; -1.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.279      ;
; -1.427 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.415      ; 1.282      ;
; -1.422 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.310      ;
; -1.417 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.315      ;
; -1.401 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.438      ; 1.331      ;
; 0.365  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.018      ;
; 0.371  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.024      ;
; 0.372  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.025      ;
; 0.393  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.046      ;
; 0.395  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.048      ;
; 0.398  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.051      ;
; 0.401  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.054      ;
; 0.403  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.424      ; 1.049      ;
; 0.405  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.431      ; 1.058      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11001                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                        ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.769 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.093      ; 3.676      ;
; 0.440  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.695      ;
; 0.442  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.697      ;
; 0.452  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.708      ;
; 0.623  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.195     ; 1.561      ;
; 0.652  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.909      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.909      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.909      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.653  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.908      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.910      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.910      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.654  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.909      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.911      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.655  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.910      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.912      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.912      ;
; 0.656  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.912      ;
; 0.658  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.913      ;
; 0.659  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.915      ;
; 0.659  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.914      ;
; 0.669  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.924      ;
; 0.672  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 0.928      ;
; 0.681  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 0.936      ;
; 0.969  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.225      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.226      ;
; 0.970  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.225      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.227      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.227      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.971  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.226      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.972  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.227      ;
; 0.973  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.229      ;
; 0.973  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.229      ;
; 0.975  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.235      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.236      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.235      ;
; 0.980  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.240      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.237      ;
; 0.981  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.236      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.238      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.237      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.239      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.241      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.240      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.240      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.242      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.242      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.241      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.243      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.242      ;
; 0.990  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.245      ;
; 0.991  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.247      ;
; 0.991  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.246      ;
; 0.999  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.255      ;
; 1.004  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.260      ;
; 1.086  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.346      ;
; 1.090  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.346      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.347      ;
; 1.091  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.351      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.348      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.348      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.092  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.347      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.093  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.348      ;
; 1.094  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.350      ;
; 1.094  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.350      ;
; 1.095  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.351      ;
; 1.096  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.353      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.353      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.097  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.352      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.098  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.353      ;
; 1.099  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.355      ;
; 1.101  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.361      ;
; 1.101  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.361      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.362      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.366      ;
; 1.106  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.074      ; 1.366      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.363      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.107  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.362      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.364      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.363      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.367      ;
; 1.111  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.366      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.368      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.070      ; 1.368      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.069      ; 1.367      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                             ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.341 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.997      ;
; 0.341 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 0.997      ;
; 0.345 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.433      ; 1.000      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.005      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.006      ;
; 0.349 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.005      ;
; 0.350 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.006      ;
; 0.351 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.008      ;
; 0.351 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.007      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.008      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.008      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.011      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.010      ;
; 0.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.013      ;
; 0.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.014      ;
; 0.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.015      ;
; 0.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.017      ;
; 0.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.017      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.019      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.018      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.019      ;
; 0.363 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.010      ;
; 0.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.021      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.024      ;
; 0.369 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.016      ;
; 0.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.028      ;
; 0.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.029      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.030      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.031      ;
; 0.374 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.031      ;
; 0.376 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[3]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.024      ;
; 0.377 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.425      ; 1.024      ;
; 0.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.036      ;
; 0.378 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.036      ;
; 0.380 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.028      ;
; 0.380 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.037      ;
; 0.381 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.029      ;
; 0.382 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[2]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.030      ;
; 0.382 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.030      ;
; 0.383 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.040      ;
; 0.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.042      ;
; 0.385 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.043      ;
; 0.386 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.034      ;
; 0.387 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.035      ;
; 0.387 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.045      ;
; 0.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.046      ;
; 0.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.048      ;
; 0.393 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~portb_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.429      ; 1.044      ;
; 0.394 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.394 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.394 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.669      ;
; 0.394 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.436      ; 1.052      ;
; 0.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.396 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.432      ; 1.050      ;
; 0.396 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.087      ; 0.669      ;
; 0.397 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.426      ; 1.045      ;
; 0.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.420      ; 1.042      ;
; 0.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.435      ; 1.057      ;
; 0.401 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.434      ; 1.057      ;
; 0.406 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.428      ; 1.056      ;
; 0.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.420      ; 1.050      ;
; 0.409 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_address_reg0         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.431      ; 1.062      ;
; 0.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.089      ; 0.685      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                    ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                    ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                    ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_display_active_reg                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|playfield_display_active_reg                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vsync_reg                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[7]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[6]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[5]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[4]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[2]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[1]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[0]                        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|low_addressa[0]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|full_dff                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.412 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_request_reg                                                                                      ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.414 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.674      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.674      ;
; 0.564 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                              ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.819      ;
; 0.605 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.860      ;
; 0.616 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.871      ;
; 0.621 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.877      ;
; 0.628 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.884      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.644 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.902      ;
; 0.646 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.900      ;
; 0.647 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.903      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.649 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.905      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.906      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 0.904      ;
; 0.650 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.905      ;
; 0.651 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.907      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.663 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.666 ; seq_reg[7]                                                                                             ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.921      ;
; 0.671 ; seq_reg[4]                                                                                             ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.926      ;
; 0.725 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.980      ;
; 0.746 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.002      ;
; 0.794 ; seq_reg[5]                                                                                             ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.049      ;
; 0.832 ; seq_reg[3]                                                                                             ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.087      ;
; 0.850 ; sdram_request_complete_reg                                                                             ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.105      ;
; 0.865 ; seq_reg[9]                                                                                             ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.122      ;
; 0.867 ; seq_reg[9]                                                                                             ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.124      ;
; 0.868 ; seq_reg[11]                                                                                            ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.123      ;
; 0.868 ; seq_reg[0]                                                                                             ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.123      ;
; 0.877 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.132      ;
; 0.889 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.144      ;
; 0.893 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.150      ;
; 0.902 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.158      ;
; 0.915 ; seq_reg[10]                                                                                            ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.067      ; 1.168      ;
; 0.942 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.198      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.962 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.218      ;
; 0.962 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.217      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.219      ;
; 0.964 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.220      ;
; 0.973 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.229      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.976 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.232      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 0.978 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.234      ;
; 0.979 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.233      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.981 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.237      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.238      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.257      ;
; 1.006 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                                                             ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.261      ;
; 1.026 ; seq_reg[6]                                                                                             ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.281      ;
; 1.040 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.292      ;
; 1.042 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.294      ;
; 1.064 ; seq_reg[2]                                                                                             ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.319      ;
; 1.074 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.331      ;
; 1.082 ; seq_reg[1]                                                                                             ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.337      ;
; 1.083 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.339      ;
; 1.084 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.340      ;
; 1.085 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.341      ;
; 1.088 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.344      ;
; 1.089 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.345      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.347      ;
; 1.090 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.346      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.355      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.358      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.359      ;
; 1.104 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.360      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.107 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.363      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.364      ;
; 1.153 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.411      ;
; 1.166 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.421      ;
; 1.194 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.153      ; 1.642      ;
; 1.204 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.458      ;
; 1.206 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.463      ;
; 1.210 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.466      ;
; 1.211 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.467      ;
; 1.212 ; seq_reg[1]                                                                                             ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.462      ;
; 1.215 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.471      ;
; 1.216 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.472      ;
; 1.218 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.466      ;
; 1.221 ; sdram_request_reg                                                                                      ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.074      ; 1.481      ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                     ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.413 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.413 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.691 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.946      ;
; 0.808 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 1.064      ;
; 0.810 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 1.066      ;
; 0.985 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.240      ;
; 1.006 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.261      ;
; 1.012 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 1.268      ;
; 1.013 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.268      ;
; 1.038 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.293      ;
; 1.168 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 1.426      ;
; 1.272 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 1.733      ;
; 1.272 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 1.733      ;
; 1.334 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.165      ; 1.795      ;
; 1.340 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 1.595      ;
; 1.396 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 1.654      ;
; 1.397 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 1.655      ;
; 1.439 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.162      ; 1.897      ;
; 1.882 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.140      ;
; 1.903 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.161      ;
; 1.991 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.450      ;
; 2.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.495      ;
; 2.069 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.529      ;
; 2.100 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.563      ;
; 2.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.567      ;
; 2.116 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.374      ;
; 2.122 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.585      ;
; 2.130 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.593      ;
; 2.133 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.596      ;
; 2.137 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.395      ;
; 2.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.635      ;
; 2.199 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.658      ;
; 2.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.666      ;
; 2.243 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.706      ;
; 2.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.724      ;
; 2.276 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.534      ;
; 2.280 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.162      ; 2.738      ;
; 2.280 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.162      ; 2.738      ;
; 2.283 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.746      ;
; 2.297 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 2.555      ;
; 2.301 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.760      ;
; 2.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.765      ;
; 2.307 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.766      ;
; 2.326 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.789      ;
; 2.331 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.791      ;
; 2.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 2.820      ;
; 2.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 2.823      ;
; 2.407 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.867      ;
; 2.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.886      ;
; 2.432 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.891      ;
; 2.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.912      ;
; 2.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.917      ;
; 2.463 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.922      ;
; 2.491 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.950      ;
; 2.492 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.951      ;
; 2.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.953      ;
; 2.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.955      ;
; 2.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.955      ;
; 2.499 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.958      ;
; 2.499 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.958      ;
; 2.499 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.958      ;
; 2.514 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.973      ;
; 2.524 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 2.983      ;
; 2.526 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.989      ;
; 2.532 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 2.995      ;
; 2.533 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 2.993      ;
; 2.537 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.000      ;
; 2.540 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.067      ; 2.793      ;
; 2.548 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.007      ;
; 2.549 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.012      ;
; 2.581 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.044      ;
; 2.583 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.164      ; 3.043      ;
; 2.603 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.059      ;
; 2.617 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.080      ;
; 2.635 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.094      ;
; 2.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.126      ;
; 2.707 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.170      ;
; 2.713 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.172      ;
; 2.743 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.206      ;
; 2.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.204      ;
; 2.746 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.205      ;
; 2.750 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.209      ;
; 2.750 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.209      ;
; 2.755 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.214      ;
; 2.756 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.215      ;
; 2.760 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.219      ;
; 2.760 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.219      ;
; 2.768 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.227      ;
; 2.774 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.237      ;
; 2.778 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.237      ;
; 2.784 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.247      ;
; 2.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.245      ;
; 2.787 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.246      ;
; 2.791 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.250      ;
; 2.791 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.250      ;
; 2.809 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.163      ; 3.268      ;
; 2.810 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.273      ;
; 2.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.167      ; 3.296      ;
; 2.856 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.067      ; 3.109      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.635 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.504     ; 1.023      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.220      ; 3.514      ;
; -2.397 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.223      ; 3.517      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.217      ; 3.401      ;
; -2.222 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.220      ; 3.404      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.283      ; 4.197      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.288      ; 4.202      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
; -0.150 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.276      ; 4.190      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                   ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.856      ;
; 7.700 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.782      ;
; 7.700 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.782      ;
; 8.071 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 3.407      ;
; 8.073 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.401      ;
; 8.073 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.182     ; 3.401      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[6]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[5]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[7]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[4]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[2]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[1]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[3]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.413      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.408      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[2]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[3]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[1]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[7]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[4]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[6]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[0]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.412      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[16]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[17]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[18]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[19]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[6]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[4]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[7]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1]                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.410      ;
; 8.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.411      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.407      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.403      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.402      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.402      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.172     ; 3.403      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.171     ; 3.404      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[1]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.166     ; 3.409      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.407      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.410      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.402      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.400      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
; 8.081 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 3.413      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                           ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.012 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.262     ; 3.259      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.275      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.275      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.274      ;
; 8.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.184     ; 3.274      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.185     ; 3.270      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.269      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.186     ; 3.269      ;
; 8.100 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.321     ; 3.111      ;
; 8.103 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.328     ; 3.101      ;
; 8.105 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.105      ;
; 8.105 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.105      ;
; 8.105 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.322     ; 3.105      ;
; 8.105 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.263      ;
; 8.106 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.263      ;
; 8.106 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.171     ; 3.263      ;
; 8.107 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.101      ;
; 8.107 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.101      ;
; 8.107 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.324     ; 3.101      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.258      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.258      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 3.224      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.258      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.258      ;
; 8.108 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 3.258      ;
; 8.111 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.217     ; 3.214      ;
; 8.113 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.218      ;
; 8.113 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.218      ;
; 8.113 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.211     ; 3.218      ;
; 8.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.214      ;
; 8.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.214      ;
; 8.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.213     ; 3.214      ;
; 8.121 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.314     ; 3.097      ;
; 8.121 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.098      ;
; 8.122 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.321     ; 3.089      ;
; 8.123 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.099      ;
; 8.123 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.313     ; 3.096      ;
; 8.123 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.099      ;
; 8.123 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.310     ; 3.099      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.210      ;
; 8.129 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.211      ;
; 8.130 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.210     ; 3.202      ;
; 8.131 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.212      ;
; 8.131 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.212      ;
; 8.131 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.199     ; 3.212      ;
; 8.131 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.209      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.231      ;
; 8.245 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.231      ;
; 8.331 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.026      ;
; 8.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.014      ;
; 8.354 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.014      ;
; 8.355 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.013      ;
; 8.355 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.013      ;
; 8.355 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 3.013      ;
; 8.615 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.862      ;
; 8.615 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.862      ;
; 8.615 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.862      ;
; 8.615 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.862      ;
; 8.615 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 2.866      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.863      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.863      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.863      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.863      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 2.863      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 2.856      ;
; 8.616 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.861      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.619 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.879      ;
; 8.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.856      ;
; 8.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.856      ;
; 8.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.856      ;
; 8.620 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 2.856      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 4.224      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 4.224      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 4.224      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.124 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 4.221      ;
; 13.125 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 4.221      ;
; 13.125 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 4.221      ;
; 13.125 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.183     ; 4.221      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.500 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.103      ; 3.955      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.108      ; 3.963      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
; -0.497 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.097      ; 3.952      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.351 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.413      ; 3.175      ;
; 0.353 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.416      ; 3.180      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.587 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.416      ; 3.297      ;
; 0.589 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.419      ; 3.302      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.830 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.355      ; 2.371      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.358      ; 2.377      ;
; 2.294 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.589      ; 3.180      ;
; 2.294 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.589      ; 3.180      ;
; 2.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 3.302      ;
; 2.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.592      ; 3.302      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.174      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[13]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.175      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[11]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.175      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.176      ; 3.169      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.175      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_shift_reg[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_shift_reg[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_shift_reg[4]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_shift_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
; 2.696 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_shift_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.179      ; 3.172      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.215 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.184      ; 2.694      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 2.672      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.160      ; 2.671      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.673      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.216 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.159      ; 2.670      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.678      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.678      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.678      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.678      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.164      ; 2.678      ;
; 2.219 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.167      ; 2.681      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.220 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.677      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.678      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.678      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.678      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.678      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.221 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 2.673      ;
; 2.469 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.837      ;
; 2.469 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.837      ;
; 2.469 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.837      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.838      ;
; 2.470 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.149      ; 2.838      ;
; 2.492 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.849      ;
; 2.585 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 3.041      ;
; 2.585 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.161      ; 3.041      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.161      ; 3.987      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.161      ; 3.987      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.161      ; 3.987      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
; 3.530 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.158      ; 3.984      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.596 ; 5.816        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.597 ; 5.817        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.598 ; 5.818        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.599 ; 5.819        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[3]                   ;
; 5.656 ; 5.814        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[6]                   ;
; 5.657 ; 5.815        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.720 ; 5.850        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.785 ; 5.896        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.850 ; 5.850        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.896 ; 5.896        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.535  ; 8.755        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.657  ; 8.787        ; 0.130          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.677  ; 8.865        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.678  ; 8.866        ; 0.188          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.722  ; 8.833        ; 0.111          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.787  ; 8.787        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.790  ; 8.790        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.829  ; 8.829        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.830  ; 8.830        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.833  ; 8.833        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.374  ; 10.404       ; 1.030          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 9.397  ; 10.427       ; 1.030          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                 ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_ena_state                                                  ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                                    ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[0] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[1] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[2] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[3] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[4] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr13|cntr_rfo:auto_generated|counter_reg_bit[5] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[0] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4] ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_counter_state                                        ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_init_state                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reset_state                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                   ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]                                       ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                  ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[0]                                                        ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[1]                                                        ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[6]                                                        ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[7]                                                        ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[0]                                                ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                                ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000                              ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                           ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]                                                ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|sendPacketRdy                                                  ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00                          ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01                          ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.10                          ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                                          ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                                         ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC                                      ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0001             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101             ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady                    ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]                     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]                     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[2]                     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[3]                     ;
; 10.142 ; 10.362       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn                        ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                              ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                                                      ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                           ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate_state                                            ;
; 10.143 ; 10.363       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_ena_state                                        ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                             ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                          ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                          ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                          ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                          ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                          ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                               ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                                ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                                ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                                ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                                ;
; 17.260 ; 17.611       ; 0.351          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.260 ; 17.611       ; 0.351          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                                ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq             ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq               ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq                 ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq           ;
; 17.339 ; 17.559       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq               ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]       ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]           ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]           ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ;
; 17.340 ; 17.560       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]           ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]           ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]           ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]            ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]          ;
; 17.341 ; 17.561       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]          ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ;
; 17.342 ; 17.562       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ;
; 17.343 ; 17.563       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[1]             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]             ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ;
; 17.345 ; 17.565       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]       ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.594 ; 17.594       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.599 ; 17.599       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.604 ; 17.604       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.641 ; 17.641       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.641 ; 17.641       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.646 ; 17.646       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.530  ; 99.833       ; 10.303         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.864  ; 100.167      ; 10.303         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.676  ; 99.864       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.679  ; 99.867       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.796  ; 99.796       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.798  ; 99.798       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.818  ; 99.818       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.832  ; 99.832       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.833  ; 99.833       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.834  ; 99.834       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.850  ; 99.850       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.852  ; 99.852       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.912  ; 100.132      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.914  ; 100.134      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.915  ; 100.135      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.757 ; 2.936 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.704 ; 2.882 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.811 ; 3.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.790 ; 0.969 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.793 ; 0.972 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.877 ; -2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.880 ; -2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.881 ; -2.060 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.880 ; -2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.833 ; -2.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.889 ; -2.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.896 ; -2.075 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.891 ; -2.070 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.890 ; -2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.837 ; -2.962 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.173 ; -0.352 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.179 ; -0.358 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.182 ; -0.361 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.176 ; -0.355 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.361  ; 2.340  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 8.517  ; 8.983  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 5.394  ; 5.386  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.652  ; 3.570  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.701  ; 3.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.629  ; 3.699  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 9.339  ; 9.705  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 6.907  ; 6.791  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 9.339  ; 9.705  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 6.789  ; 6.698  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 6.423  ; 6.271  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 9.544  ; 9.892  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 6.321  ; 6.233  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 7.215  ; 7.038  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 6.548  ; 6.453  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 9.544  ; 9.892  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.844 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.243  ; 7.645  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.777  ; 4.704  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.243  ; 7.645  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.690  ; 4.636  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.334  ; 4.211  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.446  ; 7.832  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.238  ; 4.179  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.161  ; 5.012  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.465  ; 4.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.446  ; 7.832  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.249  ; 4.237  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.066  ; 4.045  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.476  ; 1.402  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.279  ; 2.071  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.265  ; 2.057  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.476  ; 1.402  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.881  ; 5.133  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.266  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.276  ; 2.068  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.266  ; 2.058  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.488  ; 1.414  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.893  ; 5.145  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.488  ; 1.414  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.490  ; 1.416  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.635  ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.646  ; 2.508  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.249  ; 4.674  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.241  ; 4.666  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.635  ; 1.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.463  ; 2.316  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.635  ; 2.497  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.234  ; 4.659  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.632  ; 2.494  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.240  ; 4.665  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.634  ; 2.496  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.634  ; 2.496  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.267  ; 2.059  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.278  ; 2.070  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.895  ; 5.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 7.560  ; 8.023  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.457  ; 4.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.785  ; 2.703  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.832  ; 2.746  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.759  ; 2.830  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.703  ; 4.588  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.820  ; 4.680  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.258  ; 7.598  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.703  ; 4.588  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.751  ; 4.627  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.652  ; 4.590  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.652  ; 4.590  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.516  ; 5.370  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.873  ; 4.805  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.452  ; 7.776  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.057 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.407 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.439  ; 3.317  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.863  ; 3.791  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.334  ; 6.737  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.779  ; 3.726  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.439  ; 3.317  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.347  ; 3.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.347  ; 3.287  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.232  ; 4.087  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.565  ; 3.498  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.530  ; 6.916  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.782  ; 3.771  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.596  ; 3.576  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.206  ; 6.631  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.599  ; 3.579  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.131 ; 3.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 4.077 ; 4.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 4.077 ; 4.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 4.077 ; 4.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.871 ; 7.232 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.110 ; 6.471 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.131 ; 3.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.428 ; 3.342 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.368 ; 3.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.379 ; 4.303 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.847 ; 7.208 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.059 ; 3.983 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.059 ; 3.983 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.059 ; 3.983 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.465 ; 6.826 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.035 ; 3.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.035 ; 3.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.736 ; 3.588 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.890 ; 5.814 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.437 ; 5.351 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.652 ; 9.013 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 5.467 ; 5.381 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.293 ; 2.207 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.209 ; 3.133 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.209 ; 3.133 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.209 ; 3.133 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.988 ; 6.349 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.257 ; 5.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.293 ; 2.207 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.578 ; 2.492 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.485 ; 2.337 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.499 ; 3.423 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.965 ; 6.326 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.191 ; 3.115 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.191 ; 3.115 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.191 ; 3.115 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.598 ; 5.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.169 ; 3.093 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.169 ; 3.093 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.839 ; 2.691 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.276 ; 5.200 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.836 ; 4.750 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.025 ; 8.386 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.864 ; 4.778 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.054     ; 3.140     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 4.056     ; 4.132     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 4.056     ; 4.132     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 4.056     ; 4.132     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 7.282     ; 6.921     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 6.492     ; 6.131     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.054     ; 3.140     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.327     ; 3.413     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.219     ; 3.367     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.351     ; 4.427     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 7.257     ; 6.896     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.042     ; 4.118     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.042     ; 4.118     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.042     ; 4.118     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.886     ; 6.525     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.020     ; 4.096     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.020     ; 4.096     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.582     ; 3.730     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.846     ; 5.922     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 5.367     ; 5.453     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 9.039     ; 8.678     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 5.397     ; 5.483     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.216     ; 2.302     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.185     ; 3.261     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.185     ; 3.261     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.185     ; 3.261     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.397     ; 6.036     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.639     ; 5.278     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.216     ; 2.302     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.478     ; 2.564     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.336     ; 2.484     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.469     ; 3.545     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.373     ; 6.012     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.172     ; 3.248     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.172     ; 3.248     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.172     ; 3.248     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 6.017     ; 5.656     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.150     ; 3.226     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.150     ; 3.226     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.686     ; 2.834     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.232     ; 5.308     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.764     ; 4.850     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 8.411     ; 8.050     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.793     ; 4.879     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 39.41 MHz  ; 39.41 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 107.12 MHz ; 100.0 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; limit due to minimum period restriction (tmin) ;
; 111.14 MHz ; 111.14 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 156.03 MHz ; 156.03 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 219.83 MHz ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.287 ; -242.739      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.389 ; -1.389        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.290 ; -11.505       ;
; FPGA_CLK                                                                            ; 0.066  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.609  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.403  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.522 ; -113.207      ;
; FPGA_CLK                                                                            ; -0.608 ; -0.608        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.344  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.362  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.363  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.380 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.184 ; -19.654       ;
; FPGA_CLK                                                                            ; -0.180 ; -4.667        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.019  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.381  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.519 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.411 ; -10.673       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.313  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.653  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.976  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.132  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.595  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.733  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.533  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.370  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.279 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.643 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.287 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.147     ; 1.110      ;
; -3.258 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.147     ; 1.081      ;
; -3.132 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.147     ; 0.955      ;
; -3.062 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.894      ;
; -3.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.881      ;
; -3.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.138     ; 0.871      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.158     ; 0.710      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.158     ; 0.710      ;
; -2.898 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.158     ; 0.710      ;
; -2.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.148     ; 0.711      ;
; -2.882 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 1.042      ;
; -2.860 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 1.020      ;
; -2.847 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 1.020      ;
; -2.807 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 1.030      ;
; -2.785 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 1.021      ;
; -2.737 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.897      ;
; -2.736 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.896      ;
; -2.723 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.896      ;
; -2.721 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.894      ;
; -2.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.883      ;
; -2.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.880      ;
; -2.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.880      ;
; -2.711 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.871      ;
; -2.711 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.880      ;
; -2.707 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.867      ;
; -2.700 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.873      ;
; -2.699 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.872      ;
; -2.693 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.787     ; 0.876      ;
; -2.691 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.773     ; 0.888      ;
; -2.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.787     ; 0.871      ;
; -2.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.748     ; 0.909      ;
; -2.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.787     ; 0.868      ;
; -2.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.787     ; 0.867      ;
; -2.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.900      ;
; -2.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.786     ; 0.857      ;
; -2.672 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.895      ;
; -2.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.907      ;
; -2.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.786     ; 0.855      ;
; -2.670 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.773     ; 0.867      ;
; -2.662 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.748     ; 0.884      ;
; -2.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.897      ;
; -2.660 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.786     ; 0.844      ;
; -2.658 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.881      ;
; -2.656 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.892      ;
; -2.648 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.871      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.748     ; 0.868      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.882      ;
; -2.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.869      ;
; -2.645 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.881      ;
; -2.638 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.874      ;
; -2.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.739     ; 0.859      ;
; -2.610 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.723     ; 0.857      ;
; -2.583 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.752      ;
; -2.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.751      ;
; -2.575 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.813     ; 0.732      ;
; -2.575 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.743      ;
; -2.575 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.813     ; 0.732      ;
; -2.571 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.731      ;
; -2.568 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.733      ;
; -2.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.732      ;
; -2.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.731      ;
; -2.565 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.733      ;
; -2.565 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.805     ; 0.730      ;
; -2.564 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.732      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.731      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.732      ;
; -2.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.802     ; 0.731      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.731      ;
; -2.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.801     ; 0.731      ;
; -2.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.734      ;
; -2.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.796     ; 0.732      ;
; -2.558 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.797     ; 0.731      ;
; -2.557 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.796     ; 0.731      ;
; -2.552 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.811     ; 0.711      ;
; -2.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.810     ; 0.710      ;
; -2.529 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.752      ;
; -2.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.752      ;
; -2.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.776     ; 0.710      ;
; -2.515 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.751      ;
; -2.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.733      ;
; -2.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.732      ;
; -2.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.731      ;
; -2.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.747     ; 0.731      ;
; -2.507 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.767     ; 0.710      ;
; -2.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.733      ;
; -2.489 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.749     ; 0.710      ;
; -2.487 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.748     ; 0.709      ;
; -2.478 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.714      ;
; -2.476 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.712      ;
; -2.475 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.711      ;
; -2.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.734     ; 0.710      ;
; 3.653  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 7.863      ;
; 3.734  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.133     ; 7.790      ;
; 3.830  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.133     ; 7.694      ;
; 3.851  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.132     ; 7.674      ;
; 3.854  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.132     ; 7.671      ;
; 3.874  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.130     ; 7.653      ;
; 3.930  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.137     ; 7.590      ;
; 3.947  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.130     ; 7.580      ;
; 3.952  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.141     ; 7.564      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.389 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.570     ; 1.082      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.290 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.294      ;
; -0.256 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.260      ;
; -0.250 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.234      ;
; -0.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.232      ;
; -0.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.252      ;
; -0.224 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.207      ;
; -0.221 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.204      ;
; -0.213 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.196      ;
; -0.206 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.189      ;
; -0.204 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.198      ;
; -0.201 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.195      ;
; -0.199 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.193      ;
; -0.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.178      ;
; -0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.166      ;
; -0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.173      ;
; -0.176 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.170      ;
; -0.176 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.170      ;
; -0.176 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.170      ;
; -0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.158      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.156      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.167      ;
; -0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.167      ;
; -0.172 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.176      ;
; -0.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.164      ;
; -0.166 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.170      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.159      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.169      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.159      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.169      ;
; -0.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.159      ;
; -0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.168      ;
; -0.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.167      ;
; -0.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.167      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.156      ;
; -0.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.156      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.165      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.155      ;
; -0.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.165      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.153      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.153      ;
; -0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.163      ;
; -0.158 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.162      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.161      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.161      ;
; -0.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.151      ;
; -0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.150      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.157      ;
; -0.153 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.147      ;
; -0.152 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.156      ;
; -0.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.152      ;
; -0.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.141      ;
; -0.146 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.150      ;
; -0.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.148      ;
; -0.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.148      ;
; -0.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.146      ;
; -0.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.144      ;
; -0.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.134      ;
; -0.136 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.140      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.135      ;
; -0.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.074      ;
; -0.083 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.066      ;
; -0.082 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.066      ;
; -0.076 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.060      ;
; -0.074 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.057      ;
; -0.073 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.057      ;
; -0.070 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.054      ;
; -0.063 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.046      ;
; -0.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.055      ;
; -0.060 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.064      ;
; -0.054 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.058      ;
; -0.053 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.037      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.056      ;
; -0.052 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.035      ;
; -0.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.032      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.085      ; 1.028      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.086      ; 1.027      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.105      ; 1.046      ;
; -0.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.038      ;
; -0.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 1.036      ;
; -0.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.096      ; 1.014      ;
; 0.020  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.106      ; 0.984      ;
; 5.749  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.676     ; 6.018      ;
; 5.861  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.663     ; 5.919      ;
; 6.792  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 5.296      ;
; 6.903  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 5.185      ;
; 7.196  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 4.902      ;
; 7.211  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.877      ;
; 7.247  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.841      ;
; 7.316  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 4.782      ;
; 7.357  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.731      ;
; 7.392  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.696      ;
; 7.407  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.339     ; 4.697      ;
; 7.468  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.620      ;
; 7.475  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.613      ;
; 7.501  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.587      ;
; 7.527  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.339     ; 4.577      ;
; 7.527  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.339     ; 4.577      ;
; 7.577  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.355     ; 4.511      ;
; 7.608  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.225      ; 6.033      ;
; 7.613  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.225      ; 6.028      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.066   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.877      ; 3.576      ;
; 195.451 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.273     ; 1.502      ;
; 195.606 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.175      ; 4.568      ;
; 197.076 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.839      ;
; 197.105 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.810      ;
; 197.179 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.736      ;
; 197.192 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.723      ;
; 197.193 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.722      ;
; 197.221 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.694      ;
; 197.222 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.693      ;
; 197.266 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.649      ;
; 197.291 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.624      ;
; 197.295 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.620      ;
; 197.308 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.607      ;
; 197.308 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.607      ;
; 197.309 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.606      ;
; 197.337 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.578      ;
; 197.337 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.578      ;
; 197.338 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.577      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.533      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.529      ;
; 197.407 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.508      ;
; 197.407 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.508      ;
; 197.411 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.504      ;
; 197.413 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.502      ;
; 197.424 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.491      ;
; 197.424 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.491      ;
; 197.425 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.490      ;
; 197.442 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.473      ;
; 197.453 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.462      ;
; 197.453 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.462      ;
; 197.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.461      ;
; 197.498 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.417      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.413      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.413      ;
; 197.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.392      ;
; 197.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.392      ;
; 197.527 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.388      ;
; 197.528 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.387      ;
; 197.529 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.386      ;
; 197.540 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.375      ;
; 197.540 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.375      ;
; 197.541 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.374      ;
; 197.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.373      ;
; 197.558 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.357      ;
; 197.569 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.346      ;
; 197.569 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.346      ;
; 197.570 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.345      ;
; 197.571 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.344      ;
; 197.614 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.301      ;
; 197.615 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.300      ;
; 197.618 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.297      ;
; 197.618 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.297      ;
; 197.639 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.276      ;
; 197.639 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.276      ;
; 197.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.272      ;
; 197.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.271      ;
; 197.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.270      ;
; 197.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.270      ;
; 197.656 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.259      ;
; 197.656 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.259      ;
; 197.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.258      ;
; 197.657 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.258      ;
; 197.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.257      ;
; 197.674 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.241      ;
; 197.685 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.230      ;
; 197.685 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.230      ;
; 197.686 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.229      ;
; 197.686 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.229      ;
; 197.687 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.228      ;
; 197.730 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.185      ;
; 197.731 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.184      ;
; 197.732 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.183      ;
; 197.734 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.181      ;
; 197.734 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.181      ;
; 197.755 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.160      ;
; 197.755 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.160      ;
; 197.759 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.156      ;
; 197.760 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.155      ;
; 197.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.154      ;
; 197.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.154      ;
; 197.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.154      ;
; 197.772 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.143      ;
; 197.773 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.142      ;
; 197.773 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.142      ;
; 197.774 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.141      ;
; 197.790 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.125      ;
; 197.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.143      ;
; 197.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.142      ;
; 197.801 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.114      ;
; 197.801 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.114      ;
; 197.802 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.113      ;
; 197.802 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.113      ;
; 197.803 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.112      ;
; 197.824 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.062     ; 2.113      ;
; 197.846 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.069      ;
; 197.846 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.069      ;
; 197.847 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.068      ;
; 197.848 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.067      ;
; 197.850 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.084     ; 2.065      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.609 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.931      ;
; 1.716 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.817      ;
; 1.729 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 3.811      ;
; 1.910 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.623      ;
; 2.046 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.485      ;
; 2.046 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.485      ;
; 2.154 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.379      ;
; 2.167 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.364      ;
; 2.167 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.364      ;
; 2.172 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.360      ;
; 2.214 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.317      ;
; 2.241 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.141     ; 3.288      ;
; 2.275 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.258      ;
; 2.293 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.239      ;
; 2.335 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.139     ; 3.196      ;
; 2.377 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.156      ;
; 2.411 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 3.133      ;
; 2.415 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 3.105      ;
; 2.425 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 3.119      ;
; 2.425 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 3.119      ;
; 2.450 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 3.084      ;
; 2.451 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 3.084      ;
; 2.476 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.060      ;
; 2.504 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.039      ;
; 2.523 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.138     ; 3.009      ;
; 2.546 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.998      ;
; 2.546 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.998      ;
; 2.593 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.953      ;
; 2.625 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.918      ;
; 2.670 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 2.863      ;
; 2.714 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.714 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.816      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.752 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.897      ;
; 2.789 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.859      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.794 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.852      ;
; 2.806 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.724      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.807 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.842      ;
; 2.832 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.817      ;
; 2.833 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.816      ;
; 2.835 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.814      ;
; 2.835 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.695      ;
; 2.835 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.140     ; 2.695      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.837 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.809      ;
; 2.846 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.803      ;
; 2.851 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 2.696      ;
; 2.868 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.780      ;
; 2.869 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.779      ;
; 2.878 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.771      ;
; 2.910 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.738      ;
; 2.911 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.737      ;
; 2.912 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.736      ;
; 2.917 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.732      ;
; 2.917 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.732      ;
; 2.935 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.605      ;
; 2.948 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.701      ;
; 2.948 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 2.586      ;
; 2.952 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.697      ;
; 2.954 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.695      ;
; 2.982 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 2.562      ;
; 3.002 ; SDRAM_ADDR[11]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.541      ;
; 3.016 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.570     ; 1.083      ;
; 3.067 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.473      ;
; 3.067 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.473      ;
; 3.076 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 2.594      ;
; 3.100 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 2.443      ;
; 3.116 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.533      ;
; 3.143 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.505      ;
; 3.168 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.482      ;
; 3.168 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 2.482      ;
; 3.172 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.475      ;
; 3.172 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.475      ;
; 3.172 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.475      ;
; 3.174 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.135     ; 2.473      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.403  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.972     ;
; 3.432  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.943     ;
; 3.519  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.856     ;
; 3.548  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.827     ;
; 3.566  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.809     ;
; 3.595  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.780     ;
; 3.616  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.759     ;
; 3.645  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.730     ;
; 3.648  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.727     ;
; 3.677  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.698     ;
; 3.682  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.693     ;
; 3.692  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.683     ;
; 3.711  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.664     ;
; 3.721  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.654     ;
; 3.732  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.643     ;
; 3.761  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.614     ;
; 3.764  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.611     ;
; 3.793  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.582     ;
; 3.808  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.567     ;
; 3.837  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.538     ;
; 4.039  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.336     ;
; 4.202  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.173     ;
; 4.224  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 13.150     ;
; 4.252  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.123     ;
; 4.253  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 13.121     ;
; 4.284  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.091     ;
; 4.328  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 13.047     ;
; 4.340  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 13.034     ;
; 4.369  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 13.005     ;
; 4.561  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.814     ;
; 4.724  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.651     ;
; 4.774  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.601     ;
; 4.806  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.569     ;
; 4.850  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.525     ;
; 4.860  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 12.514     ;
; 5.032  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.343     ;
; 5.195  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.180     ;
; 5.245  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.130     ;
; 5.277  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.098     ;
; 5.321  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 12.054     ;
; 5.382  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 11.992     ;
; 5.748  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.569     ; 1.289      ;
; 5.847  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 11.533     ;
; 5.853  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 11.521     ;
; 5.876  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 11.504     ;
; 5.963  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 11.417     ;
; 5.992  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 11.388     ;
; 6.232  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 11.143     ;
; 6.395  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 10.980     ;
; 6.445  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 10.930     ;
; 6.477  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 10.898     ;
; 6.483  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 10.897     ;
; 6.521  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.155     ; 10.854     ;
; 7.005  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 10.375     ;
; 7.053  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.156     ; 10.321     ;
; 7.476  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 9.904      ;
; 8.623  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.843      ;
; 8.652  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.814      ;
; 8.676  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 8.704      ;
; 8.716  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.750      ;
; 8.739  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.727      ;
; 8.743  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.723      ;
; 8.745  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.721      ;
; 8.745  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.719      ;
; 8.768  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.698      ;
; 8.772  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.694      ;
; 8.774  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.690      ;
; 8.832  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.634      ;
; 8.859  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.607      ;
; 8.861  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.605      ;
; 8.861  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.603      ;
; 8.888  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.578      ;
; 8.890  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.574      ;
; 9.028  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.436      ;
; 9.057  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.407      ;
; 9.144  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.320      ;
; 9.173  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.291      ;
; 9.259  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.207      ;
; 9.352  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.114      ;
; 9.379  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 8.087      ;
; 9.381  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 8.083      ;
; 9.664  ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 7.800      ;
; 9.698  ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.768      ;
; 9.818  ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.648      ;
; 9.830  ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.636      ;
; 9.903  ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 7.561      ;
; 10.169 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.297      ;
; 10.179 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 7.285      ;
; 10.289 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.177      ;
; 10.301 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 7.165      ;
; 10.374 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 7.090      ;
; 10.650 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 6.814      ;
; 11.382 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 6.084      ;
; 11.502 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 5.964      ;
; 11.514 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 5.952      ;
; 11.574 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 5.890      ;
; 11.850 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.066     ; 5.614      ;
; 12.048 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 5.324      ;
; 12.167 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 5.205      ;
; 12.279 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.150     ; 5.101      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                         ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.915      ;
; -1.481 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.946      ;
; -1.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.963      ;
; -1.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.963      ;
; -1.471 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.946      ;
; -1.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.947      ;
; -1.469 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.968      ;
; -1.468 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.949      ;
; -1.466 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.951      ;
; -1.463 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.964      ;
; -1.463 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.974      ;
; -1.459 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.958      ;
; -1.458 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.979      ;
; -1.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.962      ;
; -1.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.982      ;
; -1.451 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.966      ;
; -1.449 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.988      ;
; -1.439 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.998      ;
; -1.438 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 0.999      ;
; -1.437 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 0.999      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.983      ;
; -1.434 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.983      ;
; -1.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.994      ;
; -1.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.005      ;
; -1.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.006      ;
; -1.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 0.986      ;
; -1.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.987      ;
; -1.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.997      ;
; -1.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.999      ;
; -1.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 0.999      ;
; -1.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.011      ;
; -1.426 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.001      ;
; -1.425 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.002      ;
; -1.423 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.004      ;
; -1.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.996      ;
; -1.420 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.997      ;
; -1.419 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 0.998      ;
; -1.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.001      ;
; -1.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.011      ;
; -1.415 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.002      ;
; -1.415 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.012      ;
; -1.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.033      ;
; -1.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.036      ;
; -1.399 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.038      ;
; -1.398 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.038      ;
; -1.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.020      ;
; -1.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.040      ;
; -1.393 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.034      ;
; -1.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.035      ;
; -1.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.037      ;
; -1.389 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.048      ;
; -1.388 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.048      ;
; -1.387 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.050      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.051      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.051      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.051      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.041      ;
; -1.386 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.050      ;
; -1.385 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.052      ;
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.054      ;
; -1.383 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.054      ;
; -1.380 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.157      ; 1.056      ;
; -1.377 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.050      ;
; -1.375 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.052      ;
; -1.375 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.052      ;
; -1.375 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.052      ;
; -1.374 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.053      ;
; -1.366 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.061      ;
; -1.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.074      ;
; -1.319 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.108      ;
; -1.309 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.118      ;
; -1.307 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.120      ;
; -1.303 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.148      ; 1.124      ;
; -1.296 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.121      ;
; -1.288 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.129      ;
; -1.285 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.132      ;
; -1.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.184      ;
; -1.233 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.204      ;
; -1.232 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.138      ; 1.185      ;
; -1.220 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.217      ;
; -1.200 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.158      ; 1.237      ;
; 0.356  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.386      ; 0.943      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[0]                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[1]                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00011                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110111                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireCtrl                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteFullSpeedRate                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.01111                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10011                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.10111                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.11000                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|CurrState_prcTxB.00110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.608 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.598      ; 3.327      ;
; 0.405  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.638      ;
; 0.408  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.641      ;
; 0.410  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.643      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.175     ; 1.407      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.828      ;
; 0.595  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.828      ;
; 0.596  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.829      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.597  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.830      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.598  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.831      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.599  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.832      ;
; 0.600  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.833      ;
; 0.601  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.834      ;
; 0.601  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.834      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.602  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.835      ;
; 0.612  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.845      ;
; 0.616  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.849      ;
; 0.622  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 0.855      ;
; 0.877  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.116      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.116      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.116      ;
; 0.883  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.116      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.884  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.117      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.885  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.118      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.886  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.119      ;
; 0.887  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.120      ;
; 0.887  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.120      ;
; 0.888  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.121      ;
; 0.888  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.127      ;
; 0.889  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.122      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.890  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.123      ;
; 0.894  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.127      ;
; 0.895  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.128      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.896  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.129      ;
; 0.898  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.131      ;
; 0.899  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.132      ;
; 0.900  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.133      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.901  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.134      ;
; 0.904  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.137      ;
; 0.915  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.148      ;
; 0.977  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.216      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.215      ;
; 0.982  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.215      ;
; 0.983  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.216      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.217      ;
; 0.984  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.217      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.985  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.218      ;
; 0.986  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.219      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.220      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.226      ;
; 0.987  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.226      ;
; 0.988  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.227      ;
; 0.993  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.226      ;
; 0.993  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.226      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.994  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.227      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.995  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.228      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.996  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.229      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.230      ;
; 0.997  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.230      ;
; 0.998  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.231      ;
; 0.998  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.237      ;
; 0.998  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.068      ; 1.237      ;
; 0.999  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.232      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.000  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.233      ;
; 1.005  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.238      ;
; 1.006  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.062      ; 1.239      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.344 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.935      ;
; 0.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.597      ;
; 0.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.597      ;
; 0.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.597      ;
; 0.346 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.597      ;
; 0.346 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.597      ;
; 0.347 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.079      ; 0.597      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.939      ;
; 0.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.939      ;
; 0.352 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.942      ;
; 0.353 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[4]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.388      ; 0.942      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.945      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.945      ;
; 0.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.945      ;
; 0.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.946      ;
; 0.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.946      ;
; 0.356 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.946      ;
; 0.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.947      ;
; 0.357 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.948      ;
; 0.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.949      ;
; 0.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.949      ;
; 0.359 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.389      ; 0.949      ;
; 0.359 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.390      ; 0.950      ;
; 0.359 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.381      ; 0.941      ;
; 0.361 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                               ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                               ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                               ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.361 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.065      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[8]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff        ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|usedw_is_0_dff  ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|usedw_is_0_dff                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Dreg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[4]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[4]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[4]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[0]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[1]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[2]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[5]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[5]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[6]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[4]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[1]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_bitcount_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_enable                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|use_status_as_ram_address                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[14]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart|cfg_bank[14]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|break_pressed_reg                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqa_reg[1]                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|irqb_reg[1]                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
; 0.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vbi_nmi_reg                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.064      ; 0.597      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.362 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_request_reg                                                                                      ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.597      ;
; 0.373 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.608      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.608      ;
; 0.516 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                              ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.750      ;
; 0.559 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.793      ;
; 0.561 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.795      ;
; 0.568 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.802      ;
; 0.578 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.812      ;
; 0.587 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.822      ;
; 0.587 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.822      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.591 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.826      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.827      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.827      ;
; 0.592 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.826      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.593 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.828      ;
; 0.597 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.830      ;
; 0.600 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.834      ;
; 0.601 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 0.834      ;
; 0.607 ; seq_reg[7]                                                                                             ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.841      ;
; 0.607 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.842      ;
; 0.608 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 0.843      ;
; 0.612 ; seq_reg[4]                                                                                             ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.846      ;
; 0.657 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.891      ;
; 0.675 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.909      ;
; 0.737 ; seq_reg[5]                                                                                             ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 0.971      ;
; 0.772 ; seq_reg[3]                                                                                             ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.006      ;
; 0.777 ; seq_reg[11]                                                                                            ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.011      ;
; 0.787 ; sdram_request_complete_reg                                                                             ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.021      ;
; 0.789 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.023      ;
; 0.801 ; seq_reg[0]                                                                                             ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.035      ;
; 0.802 ; seq_reg[9]                                                                                             ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.037      ;
; 0.804 ; seq_reg[9]                                                                                             ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.039      ;
; 0.809 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.044      ;
; 0.813 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.047      ;
; 0.826 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.060      ;
; 0.850 ; seq_reg[10]                                                                                            ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.083      ;
; 0.871 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.106      ;
; 0.873 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.108      ;
; 0.873 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.108      ;
; 0.874 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.108      ;
; 0.876 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.111      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.878 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.113      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.115      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.115      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.116      ;
; 0.881 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.116      ;
; 0.887 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.122      ;
; 0.891 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.126      ;
; 0.891 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.126      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.892 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.127      ;
; 0.901 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.062      ; 1.134      ;
; 0.922 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                                                             ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.156      ;
; 0.924 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.159      ;
; 0.938 ; seq_reg[6]                                                                                             ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.172      ;
; 0.967 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 1.199      ;
; 0.970 ; seq_reg[2]                                                                                             ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.204      ;
; 0.970 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.061      ; 1.202      ;
; 0.972 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.207      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.212      ;
; 0.977 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.212      ;
; 0.983 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.218      ;
; 0.986 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.221      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.223      ;
; 0.988 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.223      ;
; 0.990 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.225      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.226      ;
; 0.991 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.226      ;
; 0.997 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.232      ;
; 0.997 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.232      ;
; 1.001 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.236      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.237      ;
; 1.002 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.237      ;
; 1.006 ; seq_reg[1]                                                                                             ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.240      ;
; 1.010 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.245      ;
; 1.067 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.301      ;
; 1.069 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.304      ;
; 1.082 ; sdram_request_reg                                                                                      ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.322      ;
; 1.086 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.321      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.056      ; 1.314      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.322      ;
; 1.087 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.322      ;
; 1.090 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 1.508      ;
; 1.096 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.331      ;
; 1.098 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.063      ; 1.332      ;
; 1.098 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.333      ;
; 1.098 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.064      ; 1.333      ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.363 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.363 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.597      ;
; 0.628 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 0.863      ;
; 0.739 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.973      ;
; 0.739 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 0.973      ;
; 0.893 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.128      ;
; 0.913 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.148      ;
; 0.921 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.063      ; 1.155      ;
; 0.927 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.162      ;
; 0.942 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.177      ;
; 1.071 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.308      ;
; 1.176 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.150      ; 1.607      ;
; 1.177 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.150      ; 1.608      ;
; 1.206 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.064      ; 1.441      ;
; 1.227 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.150      ; 1.658      ;
; 1.291 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.528      ;
; 1.291 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.528      ;
; 1.326 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 1.755      ;
; 1.684 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.921      ;
; 1.704 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 1.941      ;
; 1.818 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.247      ;
; 1.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.262      ;
; 1.866 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.295      ;
; 1.899 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.332      ;
; 1.909 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.342      ;
; 1.923 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.356      ;
; 1.926 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.359      ;
; 1.929 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.362      ;
; 1.936 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 2.173      ;
; 1.956 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 2.193      ;
; 1.966 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.399      ;
; 1.977 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.410      ;
; 2.001 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.430      ;
; 2.032 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.461      ;
; 2.039 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.472      ;
; 2.040 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.473      ;
; 2.046 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 2.283      ;
; 2.056 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.485      ;
; 2.056 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.485      ;
; 2.066 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.066      ; 2.303      ;
; 2.089 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.518      ;
; 2.102 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.535      ;
; 2.104 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.533      ;
; 2.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.146      ; 2.536      ;
; 2.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.146      ; 2.539      ;
; 2.125 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.554      ;
; 2.126 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.555      ;
; 2.199 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.628      ;
; 2.203 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.632      ;
; 2.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.643      ;
; 2.236 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.665      ;
; 2.236 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.665      ;
; 2.248 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.681      ;
; 2.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.681      ;
; 2.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.681      ;
; 2.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.681      ;
; 2.272 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.705      ;
; 2.276 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.705      ;
; 2.281 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.710      ;
; 2.300 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.733      ;
; 2.301 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.060      ; 2.532      ;
; 2.303 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.732      ;
; 2.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.734      ;
; 2.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.734      ;
; 2.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.734      ;
; 2.309 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.738      ;
; 2.311 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.744      ;
; 2.313 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.742      ;
; 2.321 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.750      ;
; 2.324 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.753      ;
; 2.331 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.760      ;
; 2.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.146      ; 2.763      ;
; 2.347 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.780      ;
; 2.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.843      ;
; 2.413 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.842      ;
; 2.421 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.854      ;
; 2.457 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.890      ;
; 2.468 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.901      ;
; 2.485 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.914      ;
; 2.507 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.936      ;
; 2.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.942      ;
; 2.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.938      ;
; 2.509 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.938      ;
; 2.511 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.940      ;
; 2.520 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.953      ;
; 2.526 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.955      ;
; 2.531 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.964      ;
; 2.541 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.970      ;
; 2.541 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.970      ;
; 2.546 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.975      ;
; 2.553 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.152      ; 2.986      ;
; 2.555 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.984      ;
; 2.560 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.989      ;
; 2.564 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.993      ;
; 2.570 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.999      ;
; 2.570 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 2.999      ;
; 2.575 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 3.004      ;
; 2.584 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.148      ; 3.013      ;
; 2.590 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.060      ; 2.821      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.380 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.346     ; 0.919      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.184 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.084      ; 3.166      ;
; -2.182 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.087      ; 3.167      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.016 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.082      ; 3.061      ;
; -2.014 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.085      ; 3.062      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.882      ; 3.827      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.180 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.888      ; 3.833      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
; -0.179 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 2.880      ; 3.824      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.019 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.489      ;
; 8.087 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.414      ;
; 8.087 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.414      ;
; 8.429 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.068      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.062      ;
; 8.432 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 3.062      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[7]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[8]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[9]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[10]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[11]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[12]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[13]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[14]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[15]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.066      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[8]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.066      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[11]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[8]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[9]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[14]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[15]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.073      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.073      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.073      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[8]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.066      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[8]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[9]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[10]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[11]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[12]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[14]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[15]                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.067      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[16] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[7]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[5]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[4]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[6]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[1]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.072      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[2]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[3]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[12]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[13]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[15]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[14]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[8]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[9]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[11]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.071      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.067      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|ack_error              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.070      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.067      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.067      ;
; 8.439 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.067      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 8.381 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.240     ; 2.918      ;
; 8.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 2.932      ;
; 8.444 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 2.932      ;
; 8.445 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.932      ;
; 8.445 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 2.931      ;
; 8.445 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 2.930      ;
; 8.445 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.169     ; 2.930      ;
; 8.446 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 2.932      ;
; 8.454 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.303     ; 2.780      ;
; 8.454 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.296     ; 2.787      ;
; 8.458 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.782      ;
; 8.458 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.782      ;
; 8.458 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.782      ;
; 8.459 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 2.780      ;
; 8.459 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 2.780      ;
; 8.459 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.298     ; 2.780      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.920      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.920      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.920      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.920      ;
; 8.465 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.159     ; 2.920      ;
; 8.467 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.922      ;
; 8.467 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.922      ;
; 8.468 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.921      ;
; 8.470 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 2.887      ;
; 8.470 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.196     ; 2.880      ;
; 8.471 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.297     ; 2.769      ;
; 8.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.882      ;
; 8.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.882      ;
; 8.474 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.882      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.777      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.777      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.289     ; 2.773      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.285     ; 2.777      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 2.880      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 2.880      ;
; 8.475 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 2.880      ;
; 8.476 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 2.774      ;
; 8.479 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.287     ; 2.771      ;
; 8.487 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 2.869      ;
; 8.491 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.877      ;
; 8.491 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.877      ;
; 8.491 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 2.877      ;
; 8.491 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 2.873      ;
; 8.492 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.874      ;
; 8.495 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 2.871      ;
; 8.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.895      ;
; 8.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.895      ;
; 8.662 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.715      ;
; 8.685 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.703      ;
; 8.685 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.703      ;
; 8.685 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.156     ; 2.703      ;
; 8.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.703      ;
; 8.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.155     ; 2.703      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.943 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 2.546      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.551      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.551      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.551      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.551      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.160     ; 2.551      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.157     ; 2.554      ;
; 8.945 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.161     ; 2.550      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 2.566      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
; 8.948 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 2.543      ;
+-------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.849      ;
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.849      ;
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.849      ;
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 3.852      ;
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 3.852      ;
; 13.519 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.159     ; 3.852      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
; 13.520 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.162     ; 3.848      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.411 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.602      ; 3.528      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.604      ; 3.531      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
; -0.410 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.610      ; 3.537      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.134      ; 2.843      ;
; 0.313 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.137      ; 2.846      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.137      ; 2.953      ;
; 0.537 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.140      ; 2.956      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.653 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.314      ; 2.135      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 1.658 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.316      ; 2.142      ;
; 2.027 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.537      ; 2.846      ;
; 2.027 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.537      ; 2.846      ;
; 2.245 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.540      ; 2.956      ;
; 2.245 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.540      ; 2.956      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.161      ; 2.845      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.161      ; 2.845      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.161      ; 2.845      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.161      ; 2.845      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.160      ; 2.844      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.155      ; 2.839      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
; 2.402 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.158      ; 2.842      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.398      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.398      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.398      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.398      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.397      ;
; 1.976 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.398      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.162      ; 2.421      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.140      ; 2.400      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.401      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.138      ; 2.399      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.146      ; 2.407      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.981 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.139      ; 2.400      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.405      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.405      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.405      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.405      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.143      ; 2.405      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.136      ; 2.398      ;
; 1.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.142      ; 2.404      ;
; 2.218 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.553      ;
; 2.218 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.553      ;
; 2.218 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.553      ;
; 2.218 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.553      ;
; 2.218 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.129      ; 2.553      ;
; 2.241 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.118      ; 2.565      ;
; 2.310 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.731      ;
; 2.310 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.141      ; 2.731      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.132 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.144      ; 3.557      ;
; 3.132 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.144      ; 3.557      ;
; 3.132 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.144      ; 3.557      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 3.556      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 3.556      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.142      ; 3.556      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
; 3.133 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.141      ; 3.555      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.595 ; 5.813        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.596 ; 5.814        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.597 ; 5.815        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.598 ; 5.816        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
; 5.670 ; 5.826        ; 0.156          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[14]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.733 ; 5.848        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.801 ; 5.897        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.848 ; 5.848        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.897 ; 5.897        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.533  ; 8.751        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.534  ; 8.752        ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.670  ; 8.785        ; 0.115          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.680  ; 8.866        ; 0.186          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.738  ; 8.834        ; 0.096          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.785  ; 8.785        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.791  ; 8.791        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.792  ; 8.792        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.828  ; 8.828        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.834  ; 8.834        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.336 ; 17.621       ; 2.285          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                               ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.370  ; 10.390       ; 1.020          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                    ;
; 9.423  ; 10.443       ; 1.020          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                    ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[4]                                           ;
; 10.124 ; 10.342       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByte[5]                                           ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                               ;
; 10.125 ; 10.343       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                               ;
; 10.126 ; 10.344       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ;
; 10.133 ; 10.351       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011001                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                 ;
; 10.140 ; 10.358       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                              ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                  ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1010 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[0]      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInReg[1]      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInSyncReg2[0] ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxBitsInSyncReg2[1] ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[0]                          ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                          ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                          ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                          ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                    ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                     ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[3]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[4]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[5]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[6]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[7]                                                               ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                           ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010100                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011000                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011011                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011110                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011111                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.100000                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                 ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq                      ;
; 10.141 ; 10.359       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketWEn                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                      ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[12]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[13]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[14]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[15]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[16]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[17]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[18]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[19]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[20]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[21]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[22]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[23]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_pause_counter_reg[24]                                                                                                                                           ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                    ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[1]                                                                                                                                                    ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[2]                                                                                                                                                    ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[3]                                                                                                                                                    ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                 ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                                         ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                             ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                              ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate_state                               ;
; 10.142 ; 10.360       ; 0.218          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                       ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.279 ; 17.609       ; 0.330          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.290 ; 17.620       ; 0.330          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.316 ; 17.534       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1] ;
; 17.316 ; 17.534       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3] ;
; 17.318 ; 17.536       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrConnEvtReq            ;
; 17.318 ; 17.536       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrResInReq              ;
; 17.318 ; 17.536       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrSOFReq                ;
; 17.318 ; 17.536       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransDoneReq          ;
; 17.318 ; 17.536       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|setTransReq              ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                         ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0] ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7] ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]          ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[12]          ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]          ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[8]           ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]     ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]     ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]     ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]      ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]      ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[4]         ;
; 17.320 ; 17.538       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]         ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]      ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]      ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4] ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5] ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[3]         ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[5]         ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[7]         ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[9]         ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]    ;
; 17.321 ; 17.539       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]    ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ;
; 17.322 ; 17.540       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[0]      ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0] ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7] ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[10]          ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[11]          ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]          ;
; 17.323 ; 17.541       ; 0.218          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]     ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.589 ; 17.589       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.596 ; 17.596       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.605 ; 17.605       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.637 ; 17.637       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.645 ; 17.645       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.652 ; 17.652       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.643  ; 99.844       ; 10.201         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.954  ; 100.155      ; 10.201         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.680  ; 99.866       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.681  ; 99.867       ; 0.186          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.778  ; 99.778       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.779  ; 99.779       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.828  ; 99.828       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.829  ; 99.829       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.835  ; 99.835       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.844  ; 99.844       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.856  ; 99.856       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.857  ; 99.857       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.913  ; 100.131      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.914  ; 100.132      ; 0.218          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.441 ; 2.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.423 ; 2.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.425 ; 2.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.427 ; 2.598 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.425 ; 2.596 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.375 ; 2.545 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.434 ; 2.605 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.441 ; 2.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.436 ; 2.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.435 ; 2.606 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.357 ; 3.531 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.683 ; 0.854 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.688 ; 0.859 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.691 ; 0.862 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.686 ; 0.857 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.646 ; -1.817 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.649 ; -1.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.650 ; -1.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.649 ; -1.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.604 ; -1.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.657 ; -1.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.664 ; -1.835 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.660 ; -1.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.658 ; -1.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -2.495 ; -2.660 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.132 ; -0.303 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.138 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.141 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.136 ; -0.307 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.711  ; 2.561  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.697  ; 2.547  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.006  ; 1.949  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.914  ; 5.089  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.707  ; 2.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.698  ; 2.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.925  ; 5.100  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.017  ; 1.960  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.020  ; 1.963  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.355  ; 4.688  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.018  ; 2.955  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.355  ; 4.688  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.164  ; 2.127  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.887  ; 2.766  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.007  ; 2.944  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.340  ; 4.673  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.004  ; 2.941  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.346  ; 4.679  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.006  ; 2.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.699  ; 2.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.710  ; 2.560  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.928  ; 5.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 7.733  ; 7.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 5.006  ; 4.881  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.376  ; 3.256  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.419  ; 3.299  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.312  ; 3.422  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 8.412  ; 8.632  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 6.374  ; 6.229  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 8.412  ; 8.632  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 6.247  ; 6.153  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 5.981  ; 5.751  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 8.614  ; 8.799  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 5.871  ; 5.722  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 6.735  ; 6.438  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 6.093  ; 5.923  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 8.614  ; 8.799  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.310 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 11.508 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 6.528  ; 6.689  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.456  ; 4.264  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.528  ; 6.689  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.361  ; 4.208  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.044  ; 3.820  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 6.728  ; 6.855  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.940  ; 3.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 4.831  ; 4.536  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.162  ; 3.997  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.728  ; 6.855  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.810  ; 3.831  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.676  ; 3.639  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.863  ; 6.196  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.678  ; 3.641  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 2.035  ; 1.888  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 2.034  ; 1.887  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.369  ; 1.312  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 4.250  ; 4.428  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 2.042  ; 1.895  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 2.033  ; 1.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 4.260  ; 4.438  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.379  ; 1.322  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.382  ; 1.325  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.526  ; 1.488  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.352  ; 2.291  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.718  ; 4.050  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.526  ; 1.488  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.222  ; 2.103  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.341  ; 2.280  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.702  ; 4.034  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.339  ; 2.278  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.708  ; 4.040  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.340  ; 2.279  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 2.034  ; 1.887  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 2.046  ; 1.899  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 2.045  ; 1.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 4.264  ; 4.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 6.864  ; 7.021  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 4.158  ; 4.035  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 2.592  ; 2.474  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 2.634  ; 2.516  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 2.528  ; 2.636  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.384  ; 4.206  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.509  ; 4.282  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 6.553  ; 6.689  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.384  ; 4.206  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.435  ; 4.207  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.329  ; 4.177  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.329  ; 4.177  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.163  ; 4.871  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.544  ; 4.374  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 6.743  ; 6.846  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.601 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.801 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 3.235  ; 3.017  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.627  ; 3.442  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.705  ; 5.872  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.536  ; 3.388  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.235  ; 3.017  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 3.136  ; 2.993  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.136  ; 2.993  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.990  ; 3.703  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.348  ; 3.186  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.896  ; 6.031  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 3.398  ; 3.418  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 3.265  ; 3.227  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.452  ; 5.784  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 3.267  ; 3.229  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.878 ; 2.768 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.713 ; 3.664 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.713 ; 3.664 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.713 ; 3.664 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.110 ; 6.373 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.404 ; 5.667 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.878 ; 2.768 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.156 ; 3.046 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.091 ; 2.963 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.002 ; 3.953 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.096 ; 6.359 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.700 ; 3.651 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.700 ; 3.651 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.700 ; 3.651 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.740 ; 6.003 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.679 ; 3.630 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.679 ; 3.630 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.432 ; 3.304 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.328 ; 5.279 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.963 ; 4.853 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.700 ; 7.963 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.988 ; 4.878 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.139 ; 2.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.945 ; 2.896 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.945 ; 2.896 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.945 ; 2.896 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.329 ; 5.592 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.651 ; 4.914 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.139 ; 2.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.406 ; 2.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.302 ; 2.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.222 ; 3.173 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.316 ; 5.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.933 ; 2.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.933 ; 2.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.933 ; 2.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.973 ; 5.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.913 ; 2.864 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.913 ; 2.864 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.629 ; 2.501 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.783 ; 4.734 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.428 ; 4.318 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.142 ; 7.405 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.452 ; 4.342 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.746     ; 2.856     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.654     ; 3.703     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.654     ; 3.703     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.654     ; 3.703     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 6.354     ; 6.091     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 5.646     ; 5.383     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.746     ; 2.856     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.992     ; 3.102     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.919     ; 3.047     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.919     ; 3.968     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 6.334     ; 6.071     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.646     ; 3.695     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.646     ; 3.695     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.646     ; 3.695     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.998     ; 5.735     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.626     ; 3.675     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.626     ; 3.675     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.255     ; 3.383     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 5.264     ; 5.313     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.812     ; 4.922     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.929     ; 7.666     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.840     ; 4.950     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.008     ; 2.118     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.887     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.887     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.887     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 5.573     ; 5.310     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.894     ; 4.631     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.008     ; 2.118     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.244     ; 2.354     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.133     ; 2.261     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.141     ; 3.190     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 5.554     ; 5.291     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.879     ; 2.928     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.879     ; 2.928     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.879     ; 2.928     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 5.232     ; 4.969     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.860     ; 2.909     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.860     ; 2.909     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.454     ; 2.582     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 4.719     ; 4.768     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.278     ; 4.388     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 7.372     ; 7.109     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.305     ; 4.415     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.912 ; -143.903      ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.171 ; -7.417        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -0.151 ; -0.151        ;
; FPGA_CLK                                                                            ; 0.338  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.460  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 7.080  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.024 ; -77.517       ;
; FPGA_CLK                                                                            ; -0.628 ; -0.628        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.136  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.186  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 11.423 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.230 ; -11.070       ;
; FPGA_CLK                                                                            ; 0.293  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.633  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.805  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 15.216 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.450 ; -11.700       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.044  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.890  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.062  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.698  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.654  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.801  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.592  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.380  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.338 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.267     ; 0.603      ;
; -1.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.267     ; 0.587      ;
; -1.834 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.267     ; 0.525      ;
; -1.786 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.481      ;
; -1.775 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.470      ;
; -1.774 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.469      ;
; -1.698 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.559      ;
; -1.690 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.275     ; 0.373      ;
; -1.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.274     ; 0.372      ;
; -1.688 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.274     ; 0.372      ;
; -1.685 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.374      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.544      ;
; -1.675 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.543      ;
; -1.664 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.552      ;
; -1.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.546      ;
; -1.622 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.483      ;
; -1.621 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.482      ;
; -1.614 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.482      ;
; -1.612 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.480      ;
; -1.608 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.469      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.499      ;
; -1.606 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.476      ;
; -1.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.492      ;
; -1.604 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.465      ;
; -1.603 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.471      ;
; -1.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.472      ;
; -1.602 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.470      ;
; -1.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.470      ;
; -1.599 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.080     ; 0.477      ;
; -1.598 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.468      ;
; -1.598 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.486      ;
; -1.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.490      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.461      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.488      ;
; -1.593 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.481      ;
; -1.592 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.479      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.461      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.457      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.457      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.080     ; 0.468      ;
; -1.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.457      ;
; -1.588 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.459      ;
; -1.582 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.470      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.469      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.469      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.087     ; 0.452      ;
; -1.580 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.474      ;
; -1.579 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.070     ; 0.467      ;
; -1.570 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.065     ; 0.463      ;
; -1.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.461      ;
; -1.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.460      ;
; -1.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.058     ; 0.461      ;
; -1.530 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.397      ;
; -1.529 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.396      ;
; -1.527 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.100     ; 0.385      ;
; -1.527 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.100     ; 0.385      ;
; -1.526 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.393      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.384      ;
; -1.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.387      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.386      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.385      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.388      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.386      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.386      ;
; -1.519 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.093     ; 0.384      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.384      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.384      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.384      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.384      ;
; -1.513 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.097     ; 0.374      ;
; -1.513 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.098     ; 0.373      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.397      ;
; -1.503 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.397      ;
; -1.502 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.396      ;
; -1.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.386      ;
; -1.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.386      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.384      ;
; -1.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.384      ;
; -1.496 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.082     ; 0.372      ;
; -1.494 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.388      ;
; -1.489 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.075     ; 0.372      ;
; -1.486 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.373      ;
; -1.485 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.071     ; 0.372      ;
; -1.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.376      ;
; -1.480 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.374      ;
; -1.480 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.374      ;
; -1.479 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.064     ; 0.373      ;
; 7.193  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 4.371      ;
; 7.256  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 4.314      ;
; 7.312  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 4.257      ;
; 7.359  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 4.211      ;
; 7.361  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 4.209      ;
; 7.362  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.076     ; 4.207      ;
; 7.364  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 4.202      ;
; 7.383  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 4.182      ;
; 7.387  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 4.183      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.171 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.698      ;
; -0.145 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.672      ;
; -0.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.651      ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.649      ;
; -0.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.648      ;
; -0.133 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.646      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.645      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.645      ;
; -0.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.658      ;
; -0.125 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.645      ;
; -0.123 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.643      ;
; -0.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.641      ;
; -0.120 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.640      ;
; -0.119 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.633      ;
; -0.118 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.632      ;
; -0.117 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.631      ;
; -0.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.635      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.634      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.634      ;
; -0.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.634      ;
; -0.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.633      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.632      ;
; -0.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.638      ;
; -0.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.631      ;
; -0.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.630      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.628      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.628      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.627      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.627      ;
; -0.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.627      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.633      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.633      ;
; -0.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.633      ;
; -0.105 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.632      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.624      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.104 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.631      ;
; -0.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.629      ;
; -0.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.629      ;
; -0.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.642      ; 0.629      ;
; -0.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.621      ;
; -0.099 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.626      ;
; -0.098 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.625      ;
; -0.098 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.642      ; 0.626      ;
; -0.098 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.625      ;
; -0.097 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.624      ;
; -0.096 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.642      ; 0.624      ;
; -0.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.618      ;
; -0.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.618      ;
; -0.088 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.635      ; 0.609      ;
; -0.086 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.613      ;
; -0.084 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.604      ;
; -0.073 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.586      ;
; -0.071 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.584      ;
; -0.070 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.583      ;
; -0.063 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.576      ;
; -0.050 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.570      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.563      ;
; -0.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.576      ;
; -0.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.560      ;
; -0.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 0.561      ;
; -0.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.558      ;
; -0.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.571      ;
; -0.043 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.570      ;
; -0.042 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.555      ;
; -0.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.551      ;
; -0.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.549      ;
; -0.030 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.629      ; 0.545      ;
; -0.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.634      ; 0.546      ;
; -0.018 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.531      ;
; -0.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.539      ;
; -0.008 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.535      ;
; -0.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.641      ; 0.531      ;
; 0.001  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.640      ; 0.525      ;
; 8.114  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.346     ; 3.142      ;
; 8.208  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.335     ; 3.059      ;
; 8.530  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.160     ; 2.912      ;
; 8.582  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.160     ; 2.860      ;
; 8.653  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.153     ; 2.796      ;
; 8.716  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.160     ; 2.726      ;
; 8.727  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.153     ; 2.722      ;
; 8.757  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.159     ; 2.686      ;
; 8.790  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.147     ; 2.665      ;
; 8.808  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.159     ; 2.635      ;
; 8.832  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.160     ; 2.610      ;
; 8.841  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.159     ; 2.602      ;
; 8.848  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.159     ; 2.595      ;
; 8.855  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.921      ; 3.470      ;
; 8.858  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.921      ; 3.467      ;
; 8.863  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.910      ; 3.451      ;
; 8.863  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.147     ; 2.592      ;
; 8.868  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.910      ; 3.446      ;
; 8.870  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.147     ; 2.585      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.151 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -0.918     ; 0.538      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.338   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.721      ; 2.136      ;
; 197.873 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.160     ; 0.836      ;
; 198.058 ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; 0.104      ; 2.033      ;
; 198.354 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.582      ;
; 198.358 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.578      ;
; 198.422 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.514      ;
; 198.426 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.510      ;
; 198.426 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.510      ;
; 198.430 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.506      ;
; 198.438 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.498      ;
; 198.476 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.460      ;
; 198.490 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.446      ;
; 198.491 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.445      ;
; 198.494 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.442      ;
; 198.494 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.442      ;
; 198.495 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.441      ;
; 198.498 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.438      ;
; 198.506 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.430      ;
; 198.506 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.430      ;
; 198.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.394      ;
; 198.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.392      ;
; 198.553 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.383      ;
; 198.557 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.379      ;
; 198.558 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.378      ;
; 198.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.377      ;
; 198.562 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.374      ;
; 198.562 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.374      ;
; 198.563 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.373      ;
; 198.566 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.370      ;
; 198.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.362      ;
; 198.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.362      ;
; 198.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.362      ;
; 198.610 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.326      ;
; 198.610 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.326      ;
; 198.612 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.324      ;
; 198.621 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.315      ;
; 198.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.311      ;
; 198.626 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.310      ;
; 198.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.309      ;
; 198.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.308      ;
; 198.630 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.306      ;
; 198.630 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.306      ;
; 198.631 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.305      ;
; 198.632 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.304      ;
; 198.634 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.302      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.294      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.294      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.294      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.294      ;
; 198.678 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.258      ;
; 198.678 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.258      ;
; 198.680 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.256      ;
; 198.680 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.256      ;
; 198.689 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.247      ;
; 198.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.243      ;
; 198.694 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.242      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.241      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.241      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.240      ;
; 198.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.238      ;
; 198.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.238      ;
; 198.699 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.237      ;
; 198.699 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.237      ;
; 198.700 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.236      ;
; 198.702 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.234      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.226      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.226      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.226      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.226      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.225      ;
; 198.746 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.190      ;
; 198.746 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.190      ;
; 198.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.189      ;
; 198.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.188      ;
; 198.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.188      ;
; 198.757 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.179      ;
; 198.761 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.175      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.174      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.173      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.173      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.172      ;
; 198.766 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.170      ;
; 198.767 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.169      ;
; 198.767 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.169      ;
; 198.768 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.168      ;
; 198.770 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.166      ;
; 198.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.158      ;
; 198.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.158      ;
; 198.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.158      ;
; 198.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.158      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.173      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.157      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.157      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.170      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.169      ;
; 198.814 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.122      ;
; 198.814 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.122      ;
; 198.815 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.121      ;
; 198.815 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.121      ;
; 198.816 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.051     ; 1.120      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.460 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 2.143      ;
; 3.532 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 2.071      ;
; 3.534 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.073      ;
; 3.593 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.014      ;
; 3.686 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.916      ;
; 3.686 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.916      ;
; 3.688 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.915      ;
; 3.707 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.896      ;
; 3.725 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.875      ;
; 3.742 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.860      ;
; 3.742 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.860      ;
; 3.744 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.859      ;
; 3.763 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.840      ;
; 3.780 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.821      ;
; 3.796 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.809      ;
; 3.821 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[11]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.782      ;
; 3.822 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 1.772      ;
; 3.824 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.786      ;
; 3.824 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.780      ;
; 3.836 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.765      ;
; 3.836 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.769      ;
; 3.875 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.735      ;
; 3.875 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.735      ;
; 3.885 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.717      ;
; 3.912 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.111     ; 1.699      ;
; 3.931 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.679      ;
; 3.931 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.679      ;
; 3.964 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.638      ;
; 4.032 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.621      ;
; 4.033 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.568      ;
; 4.033 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.568      ;
; 4.037 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.616      ;
; 4.039 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.614      ;
; 4.039 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.570      ;
; 4.041 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.612      ;
; 4.065 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.536      ;
; 4.066 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.587      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[19]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[16]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.073 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[18]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.581      ;
; 4.075 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.110     ; 1.537      ;
; 4.089 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.512      ;
; 4.089 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.512      ;
; 4.098 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.511      ;
; 4.099 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.554      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[21]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[22]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.105 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[17]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.547      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.106 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.548      ;
; 4.120 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.483      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.137 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.515      ;
; 4.158 ; SDRAM_ADDR[11]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.451      ;
; 4.162 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.490      ;
; 4.163 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.489      ;
; 4.166 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.441      ;
; 4.169 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.112     ; 1.441      ;
; 4.184 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.470      ;
; 4.185 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.469      ;
; 4.187 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.465      ;
; 4.188 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.464      ;
; 4.189 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.463      ;
; 4.205 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.448      ;
; 4.206 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.448      ;
; 4.210 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.444      ;
; 4.212 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.116     ; 1.442      ;
; 4.226 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.383      ;
; 4.242 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.410      ;
; 4.243 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.409      ;
; 4.253 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.399      ;
; 4.254 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 1.398      ;
; 4.255 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.917     ; 0.539      ;
; 4.263 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.344      ;
; 4.263 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.344      ;
; 4.277 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.378      ;
; 4.278 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 1.377      ;
; 4.297 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.104     ; 1.369      ;
; 4.299 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.100     ; 1.371      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                       ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                           ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.080  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -0.917     ; 0.651      ;
; 9.890  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.535      ;
; 9.903  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.522      ;
; 9.953  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.472      ;
; 9.959  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.466      ;
; 9.966  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.459      ;
; 9.970  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.455      ;
; 9.983  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.442      ;
; 9.992  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.433      ;
; 10.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.420      ;
; 10.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.418      ;
; 10.019 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.406      ;
; 10.022 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.403      ;
; 10.032 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.393      ;
; 10.039 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.386      ;
; 10.061 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.364      ;
; 10.070 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.355      ;
; 10.087 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.338      ;
; 10.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.337      ;
; 10.109 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.316      ;
; 10.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.289      ;
; 10.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.173      ;
; 10.285 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.140      ;
; 10.298 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.127      ;
; 10.315 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.110      ;
; 10.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.093      ;
; 10.354 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.071      ;
; 10.354 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.071      ;
; 10.381 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.044      ;
; 10.402 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.023      ;
; 10.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 7.005      ;
; 10.483 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.942      ;
; 10.500 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.925      ;
; 10.522 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.903      ;
; 10.549 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.876      ;
; 10.647 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.778      ;
; 10.704 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.721      ;
; 10.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.658      ;
; 10.784 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.641      ;
; 10.806 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.619      ;
; 10.815 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.610      ;
; 10.833 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.592      ;
; 11.099 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.326      ;
; 11.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.288      ;
; 11.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.275      ;
; 11.210 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.219      ;
; 11.258 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 6.171      ;
; 11.332 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.093      ;
; 11.395 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.030      ;
; 11.412 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 6.013      ;
; 11.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]    ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 5.991      ;
; 11.461 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg        ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 5.964      ;
; 11.503 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 5.926      ;
; 11.671 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 5.758      ;
; 11.727 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                 ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.093     ; 5.698      ;
; 11.955 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 5.474      ;
; 12.583 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.089     ; 4.846      ;
; 12.756 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.725      ;
; 12.759 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.719      ;
; 12.769 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.712      ;
; 12.772 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.706      ;
; 12.803 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.678      ;
; 12.816 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.665      ;
; 12.825 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.656      ;
; 12.828 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.650      ;
; 12.872 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.609      ;
; 12.873 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.608      ;
; 12.873 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.608      ;
; 12.876 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.602      ;
; 12.886 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.595      ;
; 12.917 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.561      ;
; 12.920 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.561      ;
; 12.930 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.548      ;
; 12.942 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.539      ;
; 12.986 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.492      ;
; 12.990 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.491      ;
; 13.034 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.444      ;
; 13.118 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.363      ;
; 13.121 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.357      ;
; 13.165 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.316      ;
; 13.235 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.246      ;
; 13.279 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.199      ;
; 13.286 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.195      ;
; 13.289 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.189      ;
; 13.333 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.148      ;
; 13.403 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 4.078      ;
; 13.447 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 4.031      ;
; 13.570 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.911      ;
; 13.573 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 3.905      ;
; 13.617 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.864      ;
; 13.687 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.794      ;
; 13.731 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 3.747      ;
; 14.198 ; svideo_gtia:svideo|phase_count_reg[3]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.283      ;
; 14.201 ; svideo_gtia:svideo|phase_count_reg[5]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 3.277      ;
; 14.245 ; svideo_gtia:svideo|phase_count_reg[2]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.236      ;
; 14.315 ; svideo_gtia:svideo|phase_count_reg[4]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.037     ; 3.166      ;
; 14.359 ; svideo_gtia:svideo|phase_count_reg[6]                                                               ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.040     ; 3.119      ;
; 14.535 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.887      ;
; 14.607 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.815      ;
; 14.663 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg        ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.759      ;
+--------+-----------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.024 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.443      ;
; -1.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.457      ;
; -1.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.468      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.470      ;
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.472      ;
; -0.990 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.465      ;
; -0.990 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.477      ;
; -0.988 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.479      ;
; -0.988 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.467      ;
; -0.988 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.467      ;
; -0.987 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.481      ;
; -0.986 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.482      ;
; -0.985 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.469      ;
; -0.984 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.477      ;
; -0.983 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.471      ;
; -0.983 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.472      ;
; -0.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.489      ;
; -0.978 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.490      ;
; -0.978 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.477      ;
; -0.978 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                           ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.477      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.491      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.478      ;
; -0.976 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.479      ;
; -0.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.493      ;
; -0.974 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.493      ;
; -0.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.488      ;
; -0.972 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.489      ;
; -0.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.490      ;
; -0.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.484      ;
; -0.970 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.484      ;
; -0.970 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.497      ;
; -0.970 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.484      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.492      ;
; -0.969 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.492      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.968 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.493      ;
; -0.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.496      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.497      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.492      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.492      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.493      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.508      ;
; -0.958 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.509      ;
; -0.958 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.509      ;
; -0.957 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.510      ;
; -0.957 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.511      ;
; -0.954 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.507      ;
; -0.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.502      ;
; -0.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.509      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.516      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.510      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.516      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.518      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.518      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.518      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.518      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.518      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.518      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.512      ;
; -0.948 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.274      ; 0.518      ;
; -0.948 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 0.519      ;
; -0.948 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.513      ;
; -0.946 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.522      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.516      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.516      ;
; -0.944 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.517      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.519      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.519      ;
; -0.939 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.522      ;
; -0.919 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.542      ;
; -0.914 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.547      ;
; -0.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.549      ;
; -0.910 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.551      ;
; -0.906 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.549      ;
; -0.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.555      ;
; -0.900 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.555      ;
; -0.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.578      ;
; -0.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.568      ;
; -0.886 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.569      ;
; -0.885 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.583      ;
; -0.859 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.276      ; 0.609      ;
; 0.149  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.474      ;
; 0.153  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.478      ;
; 0.154  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.479      ;
; 0.161  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.486      ;
; 0.162  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.487      ;
; 0.163  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.488      ;
; 0.164  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.489      ;
; 0.166  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.221      ; 0.491      ;
; 0.169  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.495      ;
; 0.170  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.496      ;
; 0.174  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.500      ;
; 0.175  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.497      ;
; 0.175  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.501      ;
; 0.177  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.503      ;
; 0.179  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.505      ;
; 0.182  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.508      ;
; 0.183  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.505      ;
; 0.183  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.505      ;
; 0.185  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.222      ; 0.511      ;
+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                         ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.628 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.157      ; 1.779      ;
; 0.194  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.313      ;
; 0.197  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.316      ;
; 0.206  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.325      ;
; 0.207  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8     ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; -0.104     ; 0.709      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.426      ;
; 0.309  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.428      ;
; 0.313  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.432      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.450  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.452  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.575      ;
; 0.455  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.578      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.575      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.576      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.579      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.462  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.467  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.586      ;
; 0.470  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.589      ;
; 0.506  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.629      ;
; 0.509  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.632      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.515  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.516  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.635      ;
; 0.516  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.635      ;
; 0.518  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.641      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.638      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.642      ;
; 0.521  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.644      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.641      ;
; 0.522  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.039      ; 0.645      ;
; 0.523  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.642      ;
; 0.523  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.642      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.525  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.526  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.645      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                     ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.464      ;
; 0.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.465      ;
; 0.139 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.467      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.466      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.468      ;
; 0.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.468      ;
; 0.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.469      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.470      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.470      ;
; 0.142 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.470      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.471      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.471      ;
; 0.143 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.471      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.473      ;
; 0.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp1_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.474      ;
; 0.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm1_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.475      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.149 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.477      ;
; 0.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.478      ;
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.480      ;
; 0.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.480      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.481      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.481      ;
; 0.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.482      ;
; 0.154 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm2_snap_reg[2]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.482      ;
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.477      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.484      ;
; 0.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.483      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[4]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.485      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[6]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.485      ;
; 0.156 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.484      ;
; 0.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.479      ;
; 0.157 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[3]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.481      ;
; 0.157 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp2_snap_reg[0]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.486      ;
; 0.158 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[3]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.487      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.486      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.482      ;
; 0.160 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.488      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.485      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.485      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.485      ;
; 0.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm0_snap_reg[1]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.489      ;
; 0.162 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[2]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.486      ;
; 0.162 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[7]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.225      ; 0.491      ;
; 0.163 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.487      ;
; 0.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~portb_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.491      ;
; 0.165 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[1]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.488      ;
; 0.170 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.494      ;
; 0.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_address_reg0          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 0.496      ;
; 0.171 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.498      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.496      ;
; 0.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|cntr_6pf:cntr1|counter_reg_bit[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_address_reg0         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.224      ; 0.502      ;
; 0.175 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.496      ;
; 0.176 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.503      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.500      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[0]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.501      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.178 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[5]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.502      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.217      ; 0.500      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.502      ;
; 0.180 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|cntr_1ab:wr_ptr|counter_reg_bit[4]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.503      ;
; 0.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe3a[0]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~portb_address_reg0         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.226      ; 0.510      ;
; 0.181 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_datain_reg0                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 0.508      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.314      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.045      ; 0.314      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[5]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|full_dff                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[7]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[6]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[5]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[4]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[3]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[2]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[1]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|low_addressa[0]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|T[7]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleEnd                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.186 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.307      ;
; 0.317 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.437      ;
; 0.363 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.484      ;
; 0.365 ; svideo_gtia:svideo|phase_count_reg[5]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.486      ;
; 0.454 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.574      ;
; 0.458 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.578      ;
; 0.461 ; svideo_gtia:svideo|phase_count_reg[6]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.582      ;
; 0.470 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.590      ;
; 0.483 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.603      ;
; 0.539 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 0.824      ;
; 0.540 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 0.825      ;
; 0.545 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 0.668      ;
; 0.561 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 0.846      ;
; 0.604 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 0.886      ;
; 0.620 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.740      ;
; 0.644 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 0.767      ;
; 0.645 ; svideo_gtia:svideo|phase_count_reg[4]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 0.768      ;
; 0.860 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.142      ;
; 0.878 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.161      ;
; 0.885 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.008      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.173      ;
; 0.901 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.024      ;
; 0.933 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.215      ;
; 0.951 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.236      ;
; 0.953 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.238      ;
; 0.953 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.238      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.248      ;
; 0.964 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.249      ;
; 0.967 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.252      ;
; 0.977 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.260      ;
; 0.980 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.262      ;
; 0.980 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                              ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.262      ;
; 0.988 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.273      ;
; 0.988 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.111      ;
; 0.993 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.278      ;
; 1.004 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.286      ;
; 1.004 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.127      ;
; 1.006 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.291      ;
; 1.012 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.294      ;
; 1.015 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.297      ;
; 1.037 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.320      ;
; 1.038 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.320      ;
; 1.040 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.323      ;
; 1.060 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.342      ;
; 1.063 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.343      ;
; 1.063 ; svideo_gtia:svideo|phase_count_reg[3]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.186      ;
; 1.065 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.345      ;
; 1.066 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.348      ;
; 1.067 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.349      ;
; 1.069 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.351      ;
; 1.069 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.351      ;
; 1.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.358      ;
; 1.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.360      ;
; 1.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.360      ;
; 1.079 ; svideo_gtia:svideo|phase_count_reg[2]                                                            ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.039      ; 1.202      ;
; 1.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.363      ;
; 1.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.370      ;
; 1.097 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.382      ;
; 1.103 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.385      ;
; 1.103 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.386      ;
; 1.106 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.389      ;
; 1.112 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.397      ;
; 1.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.400      ;
; 1.115 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|burst_reg     ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.397      ;
; 1.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.410      ;
; 1.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.410      ;
; 1.127 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.410      ;
; 1.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.433      ;
; 1.152 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.437      ;
; 1.155 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.440      ;
; 1.166 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg     ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.446      ;
; 1.168 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.450      ;
; 1.169 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.089      ; 1.452      ;
; 1.170 ; svideo_gtia:svideo|phase_count_reg[7]                                                            ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.033      ; 1.287      ;
; 1.171 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.453      ;
; 1.172 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.454      ;
; 1.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.456      ;
; 1.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.456      ;
; 1.175 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hblank_reg    ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.460      ;
; 1.181 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.466      ;
; 1.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.475      ;
; 1.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.475      ;
; 1.194 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.476      ;
; 1.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.478      ;
; 1.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.478      ;
; 1.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.486      ;
; 1.211 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.493      ;
; 1.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.494      ;
; 1.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.499      ;
; 1.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.496      ;
; 1.214 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.496      ;
; 1.215 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.497      ;
; 1.218 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.503      ;
; 1.221 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.506      ;
; 1.233 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.515      ;
; 1.244 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.091      ; 1.529      ;
; 1.256 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.538      ;
; 1.273 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.555      ;
+-------+--------------------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_reg                                                                                      ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.254 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                              ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
; 0.263 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.383      ;
; 0.268 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.387      ;
; 0.282 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.402      ;
; 0.289 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
; 0.291 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.411      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.411      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.296 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.416      ;
; 0.299 ; seq_reg[7]                                                                                             ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.419      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.302 ; seq_reg[4]                                                                                             ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.422      ;
; 0.334 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.454      ;
; 0.344 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.464      ;
; 0.347 ; seq_reg[5]                                                                                             ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.467      ;
; 0.367 ; seq_reg[3]                                                                                             ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.487      ;
; 0.380 ; seq_reg[0]                                                                                             ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.500      ;
; 0.382 ; seq_reg[11]                                                                                            ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.501      ;
; 0.385 ; sdram_request_complete_reg                                                                             ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.504      ;
; 0.390 ; seq_reg[9]                                                                                             ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.511      ;
; 0.392 ; seq_reg[9]                                                                                             ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.513      ;
; 0.401 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.523      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.524      ;
; 0.409 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.528      ;
; 0.412 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.532      ;
; 0.415 ; seq_reg[10]                                                                                            ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.534      ;
; 0.421 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.541      ;
; 0.437 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.557      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; seq_reg[6]                                                                                             ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.564      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.448 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.567      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                                                             ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.463 ; seq_reg[2]                                                                                             ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.583      ;
; 0.472 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 0.749      ;
; 0.475 ; seq_reg[1]                                                                                             ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.595      ;
; 0.481 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.598      ;
; 0.483 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.600      ;
; 0.488 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.610      ;
; 0.496 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.618      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.640      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.640      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.640      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.643      ;
; 0.536 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.656      ;
; 0.543 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.665      ;
; 0.546 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.665      ;
; 0.553 ; seq_reg[8]                                                                                             ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.673      ;
; 0.554 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.673      ;
; 0.558 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.029      ; 0.671      ;
; 0.563 ; sdram_request_reg                                                                                      ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.040      ; 0.687      ;
; 0.564 ; seq_reg[1]                                                                                             ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.031      ; 0.679      ;
; 0.567 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.687      ;
; 0.572 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.692      ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.423 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -0.783     ; 0.496      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.624      ; 1.740      ;
; -1.230 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 1.743      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.622      ; 1.693      ;
; -1.120 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.625      ; 1.696      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.731      ; 2.191      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
; 0.293 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.725      ; 2.185      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                             ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                     ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.633 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.091     ; 1.921      ;
; 9.674 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.877      ;
; 9.674 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.094     ; 1.877      ;
; 9.847 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.098     ; 1.700      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.698      ;
; 9.850 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.097     ; 1.698      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[0]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 1.701      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[1]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[2]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[3]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[6]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[21]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[22]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[23]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[24]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[25]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[26]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[27]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[28]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[29]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 1.699      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[27]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 1.699      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.092     ; 1.699      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[2]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[3]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[7]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[4]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[6]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[10]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[12]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[15]                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack2               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.wr                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.stop                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.start                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.rd                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.mstr_ack               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[15]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[30]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.089     ; 1.702      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[31]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.703      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.705      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
; 9.854 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 1.704      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                         ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node              ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.805  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.142     ; 1.647      ;
; 9.836  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.658      ;
; 9.836  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.656      ;
; 9.836  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.656      ;
; 9.836  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.656      ;
; 9.837  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.657      ;
; 9.837  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.656      ;
; 9.837  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.656      ;
; 9.840  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.118     ; 1.639      ;
; 9.841  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.124     ; 1.632      ;
; 9.842  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.172     ; 1.581      ;
; 9.843  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 1.574      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 1.634      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 1.634      ;
; 9.844  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.119     ; 1.634      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.632      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.632      ;
; 9.845  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.120     ; 1.632      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 1.576      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 1.576      ;
; 9.846  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.173     ; 1.576      ;
; 9.847  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.574      ;
; 9.847  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.574      ;
; 9.847  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.174     ; 1.574      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.649      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.649      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.649      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.649      ;
; 9.849  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.649      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.651      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.095     ; 1.651      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.122     ; 1.625      ;
; 9.850  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.650      ;
; 9.852  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 1.567      ;
; 9.853  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.114     ; 1.630      ;
; 9.853  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.631      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.632      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.632      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.111     ; 1.632      ;
; 9.854  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.113     ; 1.630      ;
; 9.855  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 1.572      ;
; 9.855  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.573      ;
; 9.856  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.574      ;
; 9.856  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 1.572      ;
; 9.856  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.574      ;
; 9.856  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.165     ; 1.574      ;
; 9.881  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.664      ;
; 9.881  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.664      ;
; 9.946  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.548      ;
; 9.960  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.540      ;
; 9.960  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.540      ;
; 9.960  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.540      ;
; 9.960  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.540      ;
; 9.960  ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.096     ; 1.540      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.467      ;
; 10.074 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.471      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.471      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.471      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.471      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.472      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.471      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.472      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.472      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.472      ;
; 10.075 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.472      ;
; 10.076 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.094     ; 1.474      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.083     ; 1.483      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.467      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.467      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.467      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.467      ;
; 10.078 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.467      ;
+--------+------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 15.216 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.206      ;
; 15.216 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.206      ;
; 15.216 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.096     ; 2.206      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 2.203      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 2.203      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 2.203      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
; 15.217 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 2.202      ;
+--------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.162      ; 1.962      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.167      ; 1.967      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
; -0.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.161      ; 1.961      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.256      ; 1.609      ;
; 0.044 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.259      ; 1.612      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.259      ; 1.661      ;
; 0.210 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 1.664      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                         ; To Node                                                                                                                                                                                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.890 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.180      ; 1.160      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a63 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a62 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a61 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a60 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a59 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a58 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a57 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a56 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a55 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a54 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a53 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a52 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a51 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a50 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a49 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a48 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a39 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a38 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a37 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a36 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a31 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a30 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a29 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a28 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a27 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a26 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a25 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a24 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a23 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a22 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a21 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a20 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a19 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a18 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a17 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 0.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|dffe6 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 1.166      ;
; 1.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.282      ; 1.612      ;
; 1.135 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.282      ; 1.612      ;
; 1.295 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.285      ; 1.664      ;
; 1.295 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0]                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.285      ; 1.664      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[0]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[1]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[2]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[3]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[4]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[5]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[6]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[6]                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[4]                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[5]                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_count_reg[7]                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.320 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|receive_divisor_reg[2]                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.612      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.611      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.610      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.610      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[13]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.613      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.610      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[11]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.610      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[11]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.613      ;
; 1.321 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.607      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.335      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.338      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.338      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.338      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.338      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.336      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.338      ;
; 1.062 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.098      ; 1.353      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.337      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.338      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.063 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.336      ;
; 1.065 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.087      ; 1.345      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.342      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.342      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.342      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.343      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.342      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.343      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.343      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.343      ;
; 1.066 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.343      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.067 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.342      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.068 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.077      ; 1.338      ;
; 1.180 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.419      ;
; 1.180 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.419      ;
; 1.180 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.419      ;
; 1.180 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.419      ;
; 1.180 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.074      ; 1.419      ;
; 1.193 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.068      ; 1.426      ;
; 1.239 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.513      ;
; 1.239 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.513      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.698 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.978      ;
; 1.698 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.978      ;
; 1.698 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.086      ; 1.978      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.976      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.976      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|phase_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.083      ; 1.976      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
; 1.699 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; svideo_gtia:svideo|luma_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.975      ;
+-------+--------------------------------------------------------------------------------------+---------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.654 ; 5.870        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.665 ; 5.820        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[9]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[13]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.801 ; 5.870        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.824 ; 5.877        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.870 ; 5.870        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.877 ; 5.877        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.592  ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.593  ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 8.626  ; 8.810        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 8.627  ; 8.811        ; 0.184          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
; 8.738  ; 8.807        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.761  ; 8.814        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.806  ; 8.806        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.807  ; 8.807        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 8.814  ; 8.814        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|outclk                                                 ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[2]|clk                                                                                                                       ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[3]|clk                                                                                                                       ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[4]|clk                                                                                                                       ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[5]|clk                                                                                                                       ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[6]|clk                                                                                                                       ;
; 8.814  ; 8.814        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|phase_count_reg[7]|clk                                                                                                                       ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[0]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[1]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[2]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[3]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[4]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[5]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[6]|clk                                                                                                                              ;
; 8.815  ; 8.815        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo|luma_reg[7]|clk                                                                                                                              ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[0]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[1]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[2]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[3]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[4]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[5]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[6]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|luma_reg[7]                                                                                                                      ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[2]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[3]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[4]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[5]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[6]                                                                                                               ;
; 15.621 ; 17.621       ; 2.000          ; Min Period       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; svideo_gtia:svideo|phase_count_reg[7]                                                                                                               ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.380  ; 10.390       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 9.431  ; 10.441       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 10.163 ; 10.393       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_i0m3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_nsl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.168 ; 10.398       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.185 ; 10.401       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                                                                   ;
; 10.185 ; 10.401       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                                                                   ;
; 10.196 ; 10.380       ; 0.184          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.200 ; 10.430       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                                                                          ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_ena_state                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[0]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[1]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[2]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[3]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_qfo:auto_generated|counter_reg_bit[4]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[0]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[1]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[2]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[3]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[4]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[5]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[6]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr15|cntr_6jo:auto_generated|counter_reg_bit[7]                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[0]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[1]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[2]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[3]                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoData[4]                                                                                            ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type            ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                  ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_address_reg0                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_we_reg                       ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_address_reg0          ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_address_reg0         ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a35~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_sd41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~portb_address_reg0          ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~portb_address_reg0         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a32~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a33~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a39~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_kj31:auto_generated|a_dpfifo_rp31:dpfifo|altsyncram_lh81:FIFOram|ram_block1a0~porta_we_reg                         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_6i31:auto_generated|a_dpfifo_do31:dpfifo|altsyncram_pe81:FIFOram|ram_block1a0~porta_datain_reg0                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:1:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_6tc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a0~porta_datain_reg0           ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a1                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a10                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a11                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a12                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a13                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a14                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a15                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a16~porta_datain_reg0          ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a2                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a3                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a32                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a33                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a34                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a35                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a4                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a40                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a41                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a42                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a43                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a44                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a45                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a46                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a47                            ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a5                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a6                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a7                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a8                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|altshift_taps:shift_reg_rtl_0|shift_taps_u5n:auto_generated|altsyncram_7961:altsyncram4|ram_block7a9                             ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_g7a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_qg41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
+--------+--------------+----------------+-----------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.616 ; 17.616       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.338  ; 99.438       ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.462  ; 100.562      ; 10.100         ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.275  ; 99.459       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.276  ; 99.460       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.418  ; 99.418       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.420  ; 99.420       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.438  ; 99.438       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.449  ; 99.449       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.454  ; 99.454       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.455  ; 99.455       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.460  ; 99.460       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.462  ; 99.462       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.463  ; 99.463       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 100.323 ; 100.539      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 100.324 ; 100.540      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.428 ; 1.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.430 ; 1.981 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.439 ; 1.990 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.431 ; 1.982 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.430 ; 1.981 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.408 ; 1.957 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.435 ; 1.986 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.441 ; 1.992 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.437 ; 1.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.436 ; 1.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 2.033 ; 2.489 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.405 ; 0.956 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.411 ; 0.962 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.414 ; 0.965 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.409 ; 0.960 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.982 ; -1.533 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.530 ; -1.983 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.093 ; -0.644 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.651 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.653 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.097 ; -0.648 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 3.419  ; 3.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.652  ; 1.557  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.643  ; 1.548  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 1.205  ; 1.179  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.419  ; 3.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.649  ; 1.554  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.644  ; 1.549  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.427  ; 3.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 1.213  ; 1.187  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 1.214  ; 1.188  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.066  ; 3.541  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.896  ; 1.854  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.066  ; 3.541  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.057  ; 3.532  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.289  ; 1.350  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.748  ; 1.744  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.888  ; 1.846  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.054  ; 3.529  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.886  ; 1.844  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.060  ; 3.535  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.887  ; 1.845  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.645  ; 1.550  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.651  ; 1.556  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.428  ; 3.805  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 4.796  ; 5.509  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 2.757  ; 2.962  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.880  ; 1.943  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.906  ; 1.973  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 1.984  ; 1.917  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 5.311  ; 5.816  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 3.618  ; 3.651  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 5.311  ; 5.816  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 3.554  ; 3.598  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 3.347  ; 3.407  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 5.411  ; 5.920  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 3.328  ; 3.401  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 3.725  ; 3.831  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 3.431  ; 3.524  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 5.411  ; 5.920  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 10.144 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 10.618 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 4.104  ; 4.704  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.400  ; 2.525  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.104  ; 4.704  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.346  ; 2.484  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.180  ; 2.269  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 4.202  ; 4.806  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.164  ; 2.267  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.574  ; 2.711  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.268  ; 2.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.202  ; 4.806  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.323  ; 2.346  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.171  ; 2.232  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.945  ; 4.420  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.174  ; 2.235  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.682 ; 3.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 4.295 ; 4.997  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 2.266 ; 2.462  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.424 ; 1.483  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.449 ; 1.512  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 1.523 ; 1.460  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.346 ; 2.417  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.409 ; 2.474  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.104 ; 4.642  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.346 ; 2.422  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.368 ; 2.417  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 2.349 ; 2.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.349 ; 2.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.735 ; 2.828  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.450 ; 2.531  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.198 ; 4.738  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.729 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.201 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.713 ; 1.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.924 ; 2.042  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.631 ; 4.225  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.872 ; 2.004  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.713 ; 1.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.698 ; 1.795  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.698 ; 1.795  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.091 ; 2.222  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.796 ; 1.913  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.726 ; 4.323  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.076 ; 2.100  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.927 ; 1.989  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.634 ; 1.667 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.160 ; 2.159 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.160 ; 2.159 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.160 ; 2.159 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.970 ; 4.417 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.591 ; 4.038 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.634 ; 1.667 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.771 ; 1.804 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.731 ; 1.676 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.309 ; 2.308 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.963 ; 4.410 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.162 ; 2.161 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.162 ; 2.161 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.162 ; 2.161 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.780 ; 4.227 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.149 ; 2.148 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.149 ; 2.148 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.926 ; 1.871 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.131 ; 3.130 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.827 ; 2.860 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 4.932 ; 5.379 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.836 ; 2.869 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.198 ; 1.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.709 ; 1.708 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.709 ; 1.708 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.709 ; 1.708 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.512 ; 3.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.148 ; 3.595 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.198 ; 1.231 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.330 ; 1.363 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.281 ; 1.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.852 ; 1.851 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.505 ; 3.952 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.711 ; 1.710 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.711 ; 1.710 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.711 ; 1.710 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.330 ; 3.777 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.699 ; 1.698 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.699 ; 1.698 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.467 ; 1.412 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.814 ; 2.813 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.516 ; 2.549 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 4.609 ; 5.056 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.525 ; 2.558 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.711     ; 1.678     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.278     ; 2.279     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.278     ; 2.279     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.278     ; 2.279     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.562     ; 4.115     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.118     ; 3.671     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.711     ; 1.678     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.862     ; 1.829     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.743     ; 1.798     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.442     ; 2.443     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.553     ; 4.106     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.275     ; 2.276     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.275     ; 2.276     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.275     ; 2.276     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.342     ; 3.895     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.263     ; 2.264     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.263     ; 2.264     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.958     ; 2.013     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 3.243     ; 3.244     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.950     ; 2.917     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.509     ; 5.062     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.967     ; 2.934     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.274     ; 1.241     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.823     ; 1.824     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.823     ; 1.824     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.823     ; 1.824     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.098     ; 3.651     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.672     ; 3.225     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.274     ; 1.241     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.418     ; 1.385     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.290     ; 1.345     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.980     ; 1.981     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.089     ; 3.642     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.819     ; 1.820     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.819     ; 1.820     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.819     ; 1.820     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.887     ; 3.440     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.808     ; 1.809     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.808     ; 1.809     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 1.496     ; 1.551     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 2.921     ; 2.922     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 2.636     ; 2.603     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 5.180     ; 4.733     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 2.653     ; 2.620     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                   ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Clock                                                                                ; Setup    ; Hold     ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+
; Worst-case Slack                                                                     ; -3.696   ; -1.745   ; -2.397   ; -0.500  ; 5.595               ;
;  FPGA_CLK                                                                            ; 0.066    ; -0.769   ; -0.180   ; -0.500  ; 89.338              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.269    ; 0.187    ; 8.012    ; 1.062   ; 5.595               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.696   ; 0.136    ; 7.633    ; 0.890   ; 17.260              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675   ; 11.423   ; N/A      ; N/A     ; 5.720               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.870    ; 0.186    ; 13.124   ; 1.698   ; 8.533               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 17.589              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.292   ; -1.745   ; -2.397   ; 0.044   ; 9.370               ;
; Design-wide TNS                                                                      ; -287.111 ; -130.84  ; -25.473  ; -12.925 ; 0.0                 ;
;  FPGA_CLK                                                                            ; 0.000    ; -0.769   ; -4.667   ; -12.925 ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -274.155 ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.675   ; 0.000    ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000    ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A      ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -11.505  ; -130.071 ; -21.573  ; 0.000   ; 0.000               ;
+--------------------------------------------------------------------------------------+----------+----------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.753 ; 2.932 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.757 ; 2.936 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.756 ; 2.935 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.704 ; 2.882 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.764 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.771 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.767 ; 2.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.765 ; 2.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; 3.811 ; 3.944 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; 0.790 ; 0.969 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 0.796 ; 0.975 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 0.799 ; 0.978 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 0.793 ; 0.972 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -0.978 ; -1.529 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -0.990 ; -1.541 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -0.982 ; -1.533 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -0.981 ; -1.532 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -0.960 ; -1.509 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -0.986 ; -1.537 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -0.993 ; -1.544 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -0.988 ; -1.539 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -0.987 ; -1.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_DAT0       ; FPGA_CLK   ; -1.530 ; -1.983 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; dminus1       ; FPGA_CLK   ; -0.093 ; -0.303 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; -0.100 ; -0.309 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; -0.102 ; -0.312 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; -0.097 ; -0.307 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 3.037  ; 2.824  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 3.023  ; 2.810  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 2.202  ; 2.128  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 5.639  ; 5.886  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 3.034  ; 2.821  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 3.024  ; 2.811  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 5.651  ; 5.898  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 2.214  ; 2.140  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 2.216  ; 2.142  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.406  ; 3.261  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 4.975  ; 5.399  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.966  ; 5.390  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.361  ; 2.340  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.223  ; 3.069  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.394  ; 3.249  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.959  ; 5.383  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.392  ; 3.247  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.965  ; 5.389  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.393  ; 3.248  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 3.025  ; 2.812  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 3.036  ; 2.823  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 5.653  ; 5.900  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 8.517  ; 8.983  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 5.394  ; 5.386  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 3.652  ; 3.570  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 3.701  ; 3.615  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 3.629  ; 3.699  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 9.339  ; 9.705  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 6.907  ; 6.791  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 9.339  ; 9.705  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 6.789  ; 6.698  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 6.423  ; 6.271  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 9.544  ; 9.892  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 6.321  ; 6.233  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 7.215  ; 7.038  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 6.548  ; 6.453  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 9.544  ; 9.892  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 11.844 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;        ; 12.193 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 7.243  ; 7.645  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 4.777  ; 4.704  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 7.243  ; 7.645  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 4.690  ; 4.636  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 4.334  ; 4.211  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 7.446  ; 7.832  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 4.238  ; 4.179  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 5.161  ; 5.012  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 4.465  ; 4.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 7.446  ; 7.832  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 4.249  ; 4.237  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 4.063  ; 4.042  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 6.673  ; 7.097  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 4.066  ; 4.045  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                  ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]    ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]   ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]   ; FPGA_CLK   ; 1.250 ; 1.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]   ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]   ; FPGA_CLK   ; 1.241 ; 1.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]   ; FPGA_CLK   ; 0.822 ; 0.796  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]   ; FPGA_CLK   ; 3.018 ; 3.398  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]   ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]  ; FPGA_CLK   ; 1.247 ; 1.155  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[11]  ; FPGA_CLK   ; 1.242 ; 1.150  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]   ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]  ; FPGA_CLK   ; 3.024 ; 3.404  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]  ; FPGA_CLK   ; 0.828 ; 0.802  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N   ; FPGA_CLK   ; 0.830 ; 0.804  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N    ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.493 ; 1.455  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.682 ; 3.158  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.673 ; 3.149  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 0.905 ; 0.967  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.346 ; 1.346  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.486 ; 1.448  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.671 ; 3.147  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.484 ; 1.446  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.676 ; 3.152  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.485 ; 1.447  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQMH_n  ; FPGA_CLK   ; 1.243 ; 1.151  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQML_n  ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N   ; FPGA_CLK   ; 1.249 ; 1.157  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N    ; FPGA_CLK   ; 3.026 ; 3.406  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L       ; FPGA_CLK   ; 4.295 ; 4.997  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R       ; FPGA_CLK   ; 2.266 ; 2.462  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK        ; FPGA_CLK   ; 1.424 ; 1.483  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD        ; FPGA_CLK   ; 1.449 ; 1.512  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3       ; FPGA_CLK   ; 1.523 ; 1.460  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]      ; FPGA_CLK   ; 2.346 ; 2.417  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]     ; FPGA_CLK   ; 2.409 ; 2.474  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]     ; FPGA_CLK   ; 4.104 ; 4.642  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]     ; FPGA_CLK   ; 2.346 ; 2.422  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]     ; FPGA_CLK   ; 2.368 ; 2.417  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]      ; FPGA_CLK   ; 2.349 ; 2.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]     ; FPGA_CLK   ; 2.349 ; 2.410  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.735 ; 2.828  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]     ; FPGA_CLK   ; 2.450 ; 2.531  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]     ; FPGA_CLK   ; 4.198 ; 4.738  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK     ; FPGA_CLK   ; 9.729 ;        ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK     ; FPGA_CLK   ;       ; 10.201 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]      ; FPGA_CLK   ; 1.713 ; 1.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]     ; FPGA_CLK   ; 1.924 ; 2.042  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]     ; FPGA_CLK   ; 3.631 ; 4.225  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]     ; FPGA_CLK   ; 1.872 ; 2.004  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]     ; FPGA_CLK   ; 1.713 ; 1.797  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]      ; FPGA_CLK   ; 1.698 ; 1.795  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]     ; FPGA_CLK   ; 1.698 ; 1.795  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]     ; FPGA_CLK   ; 2.091 ; 2.222  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]     ; FPGA_CLK   ; 1.796 ; 1.913  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]     ; FPGA_CLK   ; 3.726 ; 4.323  ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; dminus1       ; FPGA_CLK   ; 2.076 ; 2.100  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dminus2       ; FPGA_CLK   ; 1.925 ; 1.987  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus1        ; FPGA_CLK   ; 3.698 ; 4.174  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; dplus2        ; FPGA_CLK   ; 1.927 ; 1.989  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+--------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus1       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus1      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dplus2       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; dminus2      ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; CFG_DIN      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus1       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus1      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dplus2       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; dminus2      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.09 V              ; -0.00419 V          ; 0.108 V                              ; 0.251 V                              ; 5.73e-09 s                  ; 5.85e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.69e-08 V                  ; 3.09 V             ; -0.00419 V         ; 0.108 V                             ; 0.251 V                             ; 5.73e-09 s                 ; 5.85e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.15e-09 V                   ; 3.18 V              ; -0.0303 V           ; 0.317 V                              ; 0.07 V                               ; 3.25e-10 s                  ; 3.88e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 6.15e-09 V                  ; 3.18 V             ; -0.0303 V          ; 0.317 V                             ; 0.07 V                              ; 3.25e-10 s                 ; 3.88e-10 s                 ; No                        ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.76e-08 V                   ; 3.09 V              ; -0.0166 V           ; 0.084 V                              ; 0.289 V                              ; 2.05e-09 s                  ; 1.96e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.76e-08 V                  ; 3.09 V             ; -0.0166 V          ; 0.084 V                             ; 0.289 V                             ; 2.05e-09 s                 ; 1.96e-09 s                 ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0307 V           ; 0.185 V                              ; 0.216 V                              ; 1.07e-09 s                  ; 1.08e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0307 V          ; 0.185 V                             ; 0.216 V                             ; 1.07e-09 s                 ; 1.08e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.69e-08 V                   ; 3.1 V               ; -0.0328 V           ; 0.121 V                              ; 0.141 V                              ; 7.19e-10 s                  ; 7.87e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.69e-08 V                  ; 3.1 V              ; -0.0328 V          ; 0.121 V                             ; 0.141 V                             ; 7.19e-10 s                 ; 7.87e-10 s                 ; Yes                       ; No                        ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.09 V              ; -0.00398 V          ; 0.168 V                              ; 0.263 V                              ; 6.02e-09 s                  ; 6.14e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.09 V             ; -0.00398 V         ; 0.168 V                             ; 0.263 V                             ; 6.02e-09 s                 ; 6.14e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.9e-08 V                    ; 3.1 V               ; -0.0249 V           ; 0.153 V                              ; 0.299 V                              ; 1.37e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.9e-08 V                   ; 3.1 V              ; -0.0249 V          ; 0.153 V                             ; 0.299 V                             ; 1.37e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.00169 V          ; 0.058 V                              ; 0.159 V                              ; 6.95e-09 s                  ; 7.33e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.00169 V         ; 0.058 V                             ; 0.159 V                             ; 6.95e-09 s                 ; 7.33e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.52e-07 V                   ; 3.14 V              ; -0.0428 V           ; 0.161 V                              ; 0.071 V                              ; 4.71e-10 s                  ; 4.5e-10 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 6.52e-07 V                  ; 3.14 V             ; -0.0428 V          ; 0.161 V                             ; 0.071 V                             ; 4.71e-10 s                 ; 4.5e-10 s                  ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.13e-06 V                   ; 3.08 V              ; -0.00721 V          ; 0.043 V                              ; 0.226 V                              ; 2.47e-09 s                  ; 2.5e-09 s                   ; Yes                        ; Yes                        ; 3.08 V                      ; 3.13e-06 V                  ; 3.08 V             ; -0.00721 V         ; 0.043 V                             ; 0.226 V                             ; 2.47e-09 s                 ; 2.5e-09 s                  ; Yes                       ; Yes                       ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.0139 V           ; 0.07 V                               ; 0.155 V                              ; 1.28e-09 s                  ; 1.32e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.0139 V          ; 0.07 V                              ; 0.155 V                             ; 1.28e-09 s                 ; 1.32e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.2e-06 V                    ; 3.09 V              ; -0.0146 V           ; 0.059 V                              ; 0.158 V                              ; 9.01e-10 s                  ; 9.75e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.2e-06 V                   ; 3.09 V             ; -0.0146 V          ; 0.059 V                             ; 0.158 V                             ; 9.01e-10 s                 ; 9.75e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.00144 V          ; 0.08 V                               ; 0.174 V                              ; 7.33e-09 s                  ; 7.73e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.00144 V         ; 0.08 V                              ; 0.174 V                             ; 7.33e-09 s                 ; 7.73e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.15e-06 V                   ; 3.09 V              ; -0.012 V            ; 0.078 V                              ; 0.167 V                              ; 1.65e-09 s                  ; 1.74e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 2.15e-06 V                  ; 3.09 V             ; -0.012 V           ; 0.078 V                             ; 0.167 V                             ; 1.65e-09 s                 ; 1.74e-09 s                 ; Yes                       ; Yes                       ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_B[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; VGA_B[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_B[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[0]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[1]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_L      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; AUDIO_R      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_BA[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_BA[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_RAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CAS_N  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_DQMH_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQML_n ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_CLK    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_CKE    ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[0]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[1]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[2]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[3]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[4]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[5]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[6]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[7]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.47 V              ; -0.00753 V          ; 0.323 V                              ; 0.336 V                              ; 4.77e-09 s                  ; 5.18e-09 s                  ; Yes                        ; No                         ; 3.46 V                      ; 3.12e-07 V                  ; 3.47 V             ; -0.00753 V         ; 0.323 V                             ; 0.336 V                             ; 4.77e-09 s                 ; 5.18e-09 s                 ; Yes                       ; No                        ;
; SDRAM_A[9]   ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[10]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[11]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_A[12]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CLK       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_DAT3      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; CFG_CLK      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.59e-08 V                   ; 3.58 V              ; -0.0703 V           ; 0.234 V                              ; 0.091 V                              ; 2.93e-10 s                  ; 3.09e-10 s                  ; Yes                        ; Yes                        ; 3.46 V                      ; 6.59e-08 V                  ; 3.58 V             ; -0.0703 V          ; 0.234 V                             ; 0.091 V                             ; 2.93e-10 s                 ; 3.09e-10 s                 ; Yes                       ; Yes                       ;
; CFG_CS_n     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; CFG_DOUT     ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.08e-07 V                   ; 3.48 V              ; -0.026 V            ; 0.261 V                              ; 0.327 V                              ; 1.74e-09 s                  ; 1.77e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.08e-07 V                  ; 3.48 V             ; -0.026 V           ; 0.261 V                             ; 0.327 V                             ; 1.74e-09 s                 ; 1.77e-09 s                 ; No                        ; No                        ;
; dplus1       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; dminus1      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; dplus2       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; dminus2      ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[0]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[4]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[5]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.51 V              ; -0.0513 V           ; 0.246 V                              ; 0.327 V                              ; 8.76e-10 s                  ; 8.99e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.51 V             ; -0.0513 V          ; 0.246 V                             ; 0.327 V                             ; 8.76e-10 s                 ; 8.99e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[7]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.12e-07 V                   ; 3.51 V              ; -0.0531 V           ; 0.196 V                              ; 0.245 V                              ; 6.35e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.12e-07 V                  ; 3.51 V             ; -0.0531 V          ; 0.196 V                             ; 0.245 V                             ; 6.35e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]  ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[10] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[11] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[12] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[13] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.47 V              ; -0.00704 V          ; 0.325 V                              ; 0.344 V                              ; 5.02e-09 s                  ; 5.44e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.47 V             ; -0.00704 V         ; 0.325 V                             ; 0.344 V                             ; 5.02e-09 s                 ; 5.44e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[14] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_DQ[15] ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.11e-07 V                   ; 3.5 V               ; -0.041 V            ; 0.29 V                               ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.11e-07 V                  ; 3.5 V              ; -0.041 V           ; 0.29 V                              ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
+--------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1842     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 245      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9124     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 20432068 ; 0        ; 116867   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1486291  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 19111    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25310    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1842     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 245      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9124     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 20432068 ; 0        ; 116867   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 91       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1486291  ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 19111    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 354      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 81       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 25310    ; 7        ; 42       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4806     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 741      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4806     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 21    ; 21   ;
; Unconstrained Input Port Paths  ; 21    ; 21   ;
; Unconstrained Output Ports      ; 54    ; 54   ;
; Unconstrained Output Port Paths ; 92    ; 92   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 11 22:04:36 2019
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.696
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.696      -274.155 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.675        -1.675 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.292       -11.281 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.163         0.000 FPGA_CLK 
    Info (332119):     1.269         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.870         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.745
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.745      -130.071 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.769        -0.769 FPGA_CLK 
    Info (332119):     0.341         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.413         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.413         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.635         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.397
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.397       -21.573 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.150        -3.900 FPGA_CLK 
    Info (332119):     7.633         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.012         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.124         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.500
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.500       -12.925 FPGA_CLK 
    Info (332119):     0.351         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.830         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.215         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.530         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.596
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.596         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.720         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.535         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.374         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.260         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.594         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.530         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.287
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.287      -242.739 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.389        -1.389 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -0.290       -11.505 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.066         0.000 FPGA_CLK 
    Info (332119):     1.609         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.403         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.522
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.522      -113.207 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.608        -0.608 FPGA_CLK 
    Info (332119):     0.344         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.362         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.363         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.380         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.184
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.184       -19.654 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.180        -4.667 FPGA_CLK 
    Info (332119):     8.019         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     8.381         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    13.519         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.411
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.411       -10.673 FPGA_CLK 
    Info (332119):     0.313         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.653         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.976         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.132         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.595
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.595         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.733         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.533         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.370         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.279         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.643         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.912
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.912      -143.903 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.171        -7.417 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.151        -0.151 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.338         0.000 FPGA_CLK 
    Info (332119):     3.460         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.080         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.024
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.024       -77.517 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.628        -0.628 FPGA_CLK 
    Info (332119):     0.136         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.186         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.423         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.230
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.230       -11.070 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.293         0.000 FPGA_CLK 
    Info (332119):     9.633         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.805         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    15.216         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.450
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.450       -11.700 FPGA_CLK 
    Info (332119):     0.044         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.890         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.062         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.698         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.654
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.654         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.801         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.592         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.380         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.338         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 582 megabytes
    Info: Processing ended: Wed Sep 11 22:04:46 2019
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:13


