TimeQuest Timing Analyzer report for atari5200core
Wed Sep 11 22:12:45 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 16. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 18. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 19. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 20. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 21. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 23. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 25. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 26. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 27. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 28. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 29. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 30. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 31. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 35. Setup Times
 36. Hold Times
 37. Clock to Output Times
 38. Minimum Clock to Output Times
 39. Output Enable Times
 40. Minimum Output Enable Times
 41. Output Disable Times
 42. Minimum Output Disable Times
 43. Slow 1200mV 85C Model Metastability Report
 44. Slow 1200mV 0C Model Fmax Summary
 45. Slow 1200mV 0C Model Setup Summary
 46. Slow 1200mV 0C Model Hold Summary
 47. Slow 1200mV 0C Model Recovery Summary
 48. Slow 1200mV 0C Model Removal Summary
 49. Slow 1200mV 0C Model Minimum Pulse Width Summary
 50. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 51. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 52. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 53. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 54. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 55. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 56. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 57. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 58. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 59. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 60. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 61. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 62. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 64. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 65. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 66. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 69. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 71. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 72. Setup Times
 73. Hold Times
 74. Clock to Output Times
 75. Minimum Clock to Output Times
 76. Output Enable Times
 77. Minimum Output Enable Times
 78. Output Disable Times
 79. Minimum Output Disable Times
 80. Slow 1200mV 0C Model Metastability Report
 81. Fast 1200mV 0C Model Setup Summary
 82. Fast 1200mV 0C Model Hold Summary
 83. Fast 1200mV 0C Model Recovery Summary
 84. Fast 1200mV 0C Model Removal Summary
 85. Fast 1200mV 0C Model Minimum Pulse Width Summary
 86. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 87. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 88. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 89. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 90. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
 91. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 92. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 93. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 94. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 95. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
 96. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 97. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 98. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
 99. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
100. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
103. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'
104. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
106. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
108. Setup Times
109. Hold Times
110. Clock to Output Times
111. Minimum Clock to Output Times
112. Output Enable Times
113. Minimum Output Enable Times
114. Output Disable Times
115. Minimum Output Disable Times
116. Fast 1200mV 0C Model Metastability Report
117. Multicorner Timing Analysis Summary
118. Setup Times
119. Hold Times
120. Clock to Output Times
121. Minimum Clock to Output Times
122. Board Trace Model Assignments
123. Input Transition Times
124. Slow Corner Signal Integrity Metrics
125. Fast Corner Signal Integrity Metrics
126. Setup Transfers
127. Hold Transfers
128. Recovery Transfers
129. Removal Transfers
130. Report TCCS
131. Report RSKM
132. Unconstrained Paths
133. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
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(including device programming or simulation files), and any 
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Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari5200core                                                     ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.09        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   9.1%      ;
;     Processors 3-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+-------------------------------------------------------+
; SDC File List                                         ;
+-------------------+--------+--------------------------+
; SDC File Path     ; Status ; Read at                  ;
+-------------------+--------+--------------------------+
; atari5200core.sdc ; OK     ; Wed Sep 11 22:12:36 2019 ;
+-------------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; Clock Name                                                                     ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                        ; Source                                                                           ; Targets                                                                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.640  ; 85.91 MHz ; 0.000 ; 5.820   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.640  ; 85.91 MHz ; 7.638 ; 13.458  ; 50.00      ; 1         ; 3           ; 236.2 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.460  ; 57.27 MHz ; 0.000 ; 8.730   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 11        ; 63          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                       ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                               ;                                                                                  ; { FPGA_CLK }                                                                       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                            ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                             ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note                                           ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; 42.88 MHz  ; 42.88 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 76.09 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                       ; limit due to minimum period restriction (tmin) ;
; 111.01 MHz ; 111.01 MHz      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;                                                ;
; 123.75 MHz ; 123.75 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
; 125.91 MHz ; 125.91 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                     ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.823  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.356  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.518  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 11.825 ; 0.000         ;
; FPGA_CLK                                                                       ; 93.429 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                     ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.409 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.453 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454 ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 0.454 ; 0.000         ;
; FPGA_CLK                                                                       ; 0.504 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                  ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.503  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.935  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 11.907 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.970 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.257 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.497 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.517  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.428  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.115 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.014 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.423 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.442 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                             ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.823 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 4.831      ;
; 0.995 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 4.659      ;
; 0.997 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 4.657      ;
; 1.011 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 4.516      ;
; 1.019 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 4.508      ;
; 1.073 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.582      ;
; 1.141 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 4.513      ;
; 1.157 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 4.369      ;
; 1.173 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 4.353      ;
; 1.181 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 4.345      ;
; 1.229 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 4.297      ;
; 1.363 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.178     ; 4.150      ;
; 1.371 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.284      ;
; 1.371 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.284      ;
; 1.372 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.283      ;
; 1.373 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.282      ;
; 1.414 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.180     ; 4.097      ;
; 1.431 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.156     ; 4.234      ;
; 1.433 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.156     ; 4.232      ;
; 1.433 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.156     ; 4.232      ;
; 1.436 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.156     ; 4.229      ;
; 1.436 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.156     ; 4.229      ;
; 1.455 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 4.057      ;
; 1.495 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 4.017      ;
; 1.519 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.006      ;
; 1.519 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 4.006      ;
; 1.527 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.998      ;
; 1.527 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.166     ; 3.998      ;
; 1.528 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.180     ; 3.983      ;
; 1.624 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.888      ;
; 1.624 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.888      ;
; 1.624 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.888      ;
; 1.624 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.888      ;
; 1.632 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.880      ;
; 1.632 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.880      ;
; 1.632 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.880      ;
; 1.632 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.880      ;
; 1.659 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 3.867      ;
; 1.667 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 3.859      ;
; 1.677 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.837      ;
; 1.685 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.829      ;
; 1.811 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.703      ;
; 1.819 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.695      ;
; 1.971 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 3.555      ;
; 2.080 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.157     ; 3.584      ;
; 2.082 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.157     ; 3.582      ;
; 2.101 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.411      ;
; 2.109 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.179     ; 3.403      ;
; 2.219 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.175     ; 3.297      ;
; 2.240 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.411      ;
; 2.361 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.189     ; 3.141      ;
; 2.407 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.237      ;
; 2.409 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.235      ;
; 2.410 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.234      ;
; 2.410 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.234      ;
; 2.417 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.189     ; 3.085      ;
; 2.455 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.199      ;
; 2.457 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.197      ;
; 2.457 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.197      ;
; 2.460 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.168     ; 3.193      ;
; 2.460 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.194      ;
; 2.460 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.167     ; 3.194      ;
; 2.466 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.178     ; 3.177      ;
; 2.468 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.178     ; 3.175      ;
; 2.469 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.178     ; 3.174      ;
; 2.479 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.175     ; 3.037      ;
; 2.484 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.180     ; 3.027      ;
; 2.510 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.178     ; 3.133      ;
; 2.519 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.174     ; 2.998      ;
; 2.529 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.174     ; 2.988      ;
; 2.540 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 2.986      ;
; 2.550 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.165     ; 2.976      ;
; 2.578 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.177     ; 3.066      ;
; 2.580 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.071      ;
; 2.580 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 3.071      ;
; 2.745 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 2.782      ;
; 2.753 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.168     ; 2.900      ;
; 2.756 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.164     ; 2.771      ;
; 2.773 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.157     ; 2.891      ;
; 2.773 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.157     ; 2.891      ;
; 2.788 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.189     ; 2.714      ;
; 2.798 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.189     ; 2.704      ;
; 2.809 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.176     ; 2.706      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.835 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.170     ; 2.816      ;
; 2.889 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.761      ;
; 2.889 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.761      ;
; 2.889 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.171     ; 2.761      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                         ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.356 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 9.107      ;
; 2.383 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 9.081      ;
; 2.398 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 9.060      ;
; 2.570 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 8.889      ;
; 2.912 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 8.540      ;
; 2.964 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.502      ;
; 3.083 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.383      ;
; 3.084 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 8.383      ;
; 3.149 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 8.316      ;
; 3.221 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 8.237      ;
; 3.223 ; ram_do_reg[0]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 8.236      ;
; 3.230 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 8.217      ;
; 3.240 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 8.219      ;
; 3.262 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.196     ; 8.183      ;
; 3.262 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.196     ; 8.183      ;
; 3.269 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.173      ;
; 3.269 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.173      ;
; 3.269 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[6]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.173      ;
; 3.269 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.173      ;
; 3.276 ; ram_do_reg[2]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.188      ;
; 3.284 ; ram_do_reg[6]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 8.175      ;
; 3.286 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.208     ; 8.147      ;
; 3.286 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[10]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.208     ; 8.147      ;
; 3.286 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.208     ; 8.147      ;
; 3.286 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.208     ; 8.147      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 8.166      ;
; 3.288 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.178      ;
; 3.339 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.103      ;
; 3.339 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.103      ;
; 3.339 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.103      ;
; 3.339 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposp3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.103      ;
; 3.367 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 8.099      ;
; 3.367 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.075      ;
; 3.384 ; ram_do_reg[1]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 8.075      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.394 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 8.048      ;
; 3.401 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 8.062      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[6]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[0]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[1]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[2]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[3]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[4]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.441 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[5]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.000      ;
; 3.475 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[0]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.966      ;
; 3.475 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[1]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.966      ;
; 3.513 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp3_reg[5]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.942      ;
; 3.513 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp3_reg[7]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.942      ;
; 3.521 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[6]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.921      ;
; 3.521 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[7]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.921      ;
; 3.526 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.915      ;
; 3.526 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.915      ;
; 3.526 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.915      ;
; 3.526 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.915      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[9] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[8] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.538 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.911      ;
; 3.540 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.926      ;
; 3.540 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.901      ;
; 3.540 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.901      ;
; 3.540 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.901      ;
; 3.540 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.901      ;
; 3.540 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.901      ;
; 3.569 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.195     ; 7.877      ;
; 3.569 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.195     ; 7.877      ;
; 3.571 ; ram_do_reg[5]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.893      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
; 3.575 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 7.884      ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                   ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.518  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 7.657      ;
; 9.777  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 7.398      ;
; 9.846  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 7.330      ;
; 9.919  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 7.279      ;
; 10.123 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.135     ; 7.073      ;
; 10.264 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.933      ;
; 10.294 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.903      ;
; 10.364 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.812      ;
; 10.383 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.135     ; 6.813      ;
; 10.398 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.835      ;
; 10.411 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.786      ;
; 10.427 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.748      ;
; 10.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.760      ;
; 10.474 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.701      ;
; 10.485 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.747      ;
; 10.486 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.711      ;
; 10.537 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 6.660      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.551 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.754      ;
; 10.553 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.622      ;
; 10.563 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.133     ; 6.635      ;
; 10.573 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 6.421      ;
; 10.574 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.454     ; 6.433      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.578 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.727      ;
; 10.587 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.589      ;
; 10.610 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.622      ;
; 10.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.612      ;
; 10.634 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.598      ;
; 10.686 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.546      ;
; 10.688 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.487      ;
; 10.706 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.454     ; 6.301      ;
; 10.716 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.516      ;
; 10.747 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.485      ;
; 10.758 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 6.236      ;
; 10.759 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.473      ;
; 10.759 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.454     ; 6.248      ;
; 10.763 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.412      ;
; 10.771 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.462      ;
; 10.873 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.359      ;
; 10.875 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.156     ; 6.300      ;
; 10.876 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.454     ; 6.131      ;
; 10.877 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.355      ;
; 10.881 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.352      ;
; 10.884 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.135     ; 6.312      ;
; 10.936 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 6.058      ;
; 10.971 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.465     ; 6.025      ;
; 10.983 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 6.248      ;
; 10.988 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 6.006      ;
; 11.011 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.222      ;
; 11.020 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.212      ;
; 11.030 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.155     ; 6.146      ;
; 11.037 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.195      ;
; 11.083 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.150      ;
; 11.086 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.135     ; 6.110      ;
; 11.114 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.118      ;
; 11.149 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.083      ;
; 11.163 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 6.070      ;
; 11.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.038      ;
; 11.204 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.028      ;
; 11.210 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 6.021      ;
; 11.213 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.019      ;
; 11.220 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 6.012      ;
; 11.231 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                          ; scanlines_reg                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 6.039      ;
; 11.272 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.959      ;
; 11.303 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.929      ;
; 11.339 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.894      ;
; 11.395 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.836      ;
; 11.418 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.814      ;
; 11.463 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.769      ;
; 11.464 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.769      ;
; 11.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.763      ;
; 11.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.761      ;
; 11.496 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.736      ;
; 11.499 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.734      ;
; 11.521 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.710      ;
; 11.525 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.098     ; 5.708      ;
; 11.540 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.100     ; 5.691      ;
; 11.602 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.134     ; 5.595      ;
; 11.693 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.099     ; 5.539      ;
; 11.714 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.467     ; 5.280      ;
; 11.723 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[1]                                                                                       ; scanlines_reg                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 5.547      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 11.825 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.947      ;
; 11.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.873      ;
; 11.937 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.835      ;
; 12.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.761      ;
; 12.099 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.673      ;
; 12.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.599      ;
; 12.230 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.542      ;
; 12.247 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.525      ;
; 12.321 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.451      ;
; 12.326 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.429      ;
; 12.327 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.428      ;
; 12.327 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.428      ;
; 12.342 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.430      ;
; 12.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.379      ;
; 12.377 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.378      ;
; 12.377 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.378      ;
; 12.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.268      ;
; 12.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.250      ;
; 12.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.249      ;
; 12.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.249      ;
; 12.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 8.120      ;
; 12.711 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.044      ;
; 12.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.043      ;
; 12.712 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 8.043      ;
; 12.789 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.966      ;
; 12.790 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.965      ;
; 12.790 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.965      ;
; 12.801 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.954      ;
; 12.802 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.953      ;
; 12.802 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.953      ;
; 12.888 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.864      ;
; 12.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.790      ;
; 12.993 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.762      ;
; 12.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.761      ;
; 12.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.761      ;
; 13.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.771      ;
; 13.075 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.697      ;
; 13.082 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.690      ;
; 13.141 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.614      ;
; 13.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.613      ;
; 13.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 7.613      ;
; 13.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.616      ;
; 13.179 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.593      ;
; 13.253 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.519      ;
; 13.293 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 7.459      ;
; 13.297 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.459      ;
; 13.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.411      ;
; 13.351 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.405      ;
; 13.352 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 7.402      ;
; 13.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 7.401      ;
; 13.353 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 7.401      ;
; 13.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.361      ;
; 13.406 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.366      ;
; 13.453 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.086     ; 7.165      ;
; 13.487 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.285      ;
; 13.491 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.265      ;
; 13.524 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.232      ;
; 13.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 7.217      ;
; 13.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 7.188      ;
; 13.697 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.059      ;
; 13.730 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.026      ;
; 13.731 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 7.025      ;
; 13.775 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.981      ;
; 13.785 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.971      ;
; 13.787 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.969      ;
; 13.808 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.948      ;
; 13.820 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.936      ;
; 13.833 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.939      ;
; 13.849 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.923      ;
; 13.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.882      ;
; 13.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.827      ;
; 13.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 6.792      ;
; 13.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.814      ;
; 13.955 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.801      ;
; 13.957 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.080     ; 6.797      ;
; 13.961 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.811      ;
; 13.973 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.799      ;
; 13.979 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.777      ;
; 14.002 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.770      ;
; 14.012 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.744      ;
; 14.026 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.740      ;
; 14.034 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.721      ;
; 14.047 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.725      ;
; 14.084 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.671      ;
; 14.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.667      ;
; 14.092 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.666      ;
; 14.092 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.666      ;
; 14.094 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.087     ; 6.523      ;
; 14.107 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.665      ;
; 14.123 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.649      ;
; 14.127 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.629      ;
; 14.142 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.087     ; 6.475      ;
; 14.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.596      ;
; 14.161 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.078     ; 6.595      ;
; 14.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.062     ; 6.608      ;
; 14.165 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.092     ; 6.577      ;
; 14.180 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.575      ;
; 14.192 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.079     ; 6.563      ;
; 14.202 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.556      ;
; 14.203 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.555      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                       ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 93.429  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; -1.299     ; 5.273      ;
; 97.280  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; 1.071      ; 0.990      ;
; 196.364 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.560      ;
; 196.394 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.530      ;
; 196.486 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.438      ;
; 196.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.414      ;
; 196.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.412      ;
; 196.540 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.384      ;
; 196.542 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.382      ;
; 196.596 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.328      ;
; 196.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.296      ;
; 196.632 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.292      ;
; 196.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.282      ;
; 196.656 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.268      ;
; 196.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.266      ;
; 196.672 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.252      ;
; 196.686 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.238      ;
; 196.688 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.236      ;
; 196.742 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.182      ;
; 196.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.173      ;
; 196.774 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.150      ;
; 196.774 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.150      ;
; 196.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.146      ;
; 196.788 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.136      ;
; 196.799 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.125      ;
; 196.802 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.122      ;
; 196.804 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.120      ;
; 196.818 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.106      ;
; 196.829 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.095      ;
; 196.832 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.092      ;
; 196.834 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.090      ;
; 196.888 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.036      ;
; 196.897 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.027      ;
; 196.900 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.024      ;
; 196.920 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.004      ;
; 196.920 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.004      ;
; 196.924 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 3.000      ;
; 196.925 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.999      ;
; 196.934 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.990      ;
; 196.945 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.979      ;
; 196.947 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.977      ;
; 196.948 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.976      ;
; 196.950 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.974      ;
; 196.964 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.960      ;
; 196.975 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.949      ;
; 196.977 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.947      ;
; 196.978 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.946      ;
; 196.980 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.944      ;
; 197.034 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.890      ;
; 197.038 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.886      ;
; 197.043 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.881      ;
; 197.046 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.878      ;
; 197.066 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.858      ;
; 197.066 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.858      ;
; 197.070 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.854      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.853      ;
; 197.071 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.853      ;
; 197.080 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.844      ;
; 197.091 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.833      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.831      ;
; 197.094 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.830      ;
; 197.095 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.829      ;
; 197.096 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.828      ;
; 197.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.814      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.803      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.801      ;
; 197.124 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.800      ;
; 197.125 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.799      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.798      ;
; 197.180 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.744      ;
; 197.184 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.740      ;
; 197.184 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.740      ;
; 197.189 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.735      ;
; 197.192 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.732      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.082     ; 2.707      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.712      ;
; 197.212 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.712      ;
; 197.216 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.708      ;
; 197.217 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.707      ;
; 197.217 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.707      ;
; 197.217 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.707      ;
; 197.226 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.698      ;
; 197.237 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.687      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.684      ;
; 197.239 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.685      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.681      ;
; 197.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.683      ;
; 197.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.077     ; 2.682      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                               ; To Node                                                                                                                                                                                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.409 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[1]                                                                   ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.142      ;
; 0.423 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[7]                                                                   ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.479      ; 1.156      ;
; 0.440 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.476      ; 1.170      ;
; 0.447 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                                                      ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.475      ; 1.176      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[34]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[50]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[49]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[35]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                        ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                        ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[363]                                                                                                                                        ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_reset_n_reg                                                                                                                                                                       ; sdram_reset_n_reg                                                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                                                                                                         ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_loadb2                                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                       ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                       ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                       ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                       ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                  ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                     ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                              ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                              ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|full_dff       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|full_dff                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|usedw_is_0_dff ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|usedw_is_0_dff                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[19]                                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[6]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[1]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[0]                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[22]                                                               ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[22]                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[3]                                                                ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[3]                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[15]                                                               ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[15]                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                         ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.746      ;
; 0.455 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.465 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.758      ;
; 0.494 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.787      ;
; 0.495 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.788      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.792      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.793      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.501 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.794      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.502 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.796      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.797      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.796      ;
; 0.508 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.801      ;
; 0.613 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                 ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 1.035      ;
; 0.676 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.095      ; 0.983      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.979      ;
; 0.687 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.979      ;
; 0.692 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.985      ;
; 0.694 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.986      ;
; 0.697 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.990      ;
; 0.697 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.990      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.990      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.698 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 0.991      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
; 0.699 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 0.992      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                             ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.466 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.502 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.794      ;
; 0.526 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.818      ;
; 0.529 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.821      ;
; 0.595 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.887      ;
; 0.598 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.890      ;
; 0.642 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.934      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.983      ;
; 0.707 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.999      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.036      ;
; 0.745 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.036      ;
; 0.753 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.045      ;
; 0.757 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.049      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.049      ;
; 0.775 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.067      ;
; 0.799 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.091      ;
; 0.805 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.097      ;
; 0.811 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.103      ;
; 0.870 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.162      ;
; 0.877 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.168      ;
; 0.880 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.172      ;
; 0.886 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.178      ;
; 0.934 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.225      ;
; 0.935 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.226      ;
; 0.960 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.252      ;
; 0.964 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.256      ;
; 0.970 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.261      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.300      ;
; 1.010 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.302      ;
; 1.065 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.357      ;
; 1.078 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.371      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.099 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.391      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.108 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.400      ;
; 1.108 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.400      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.123 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.415      ;
; 1.140 ; sdram_request_complete_reg                                ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.432      ;
; 1.188 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.480      ;
; 1.197 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.488      ;
; 1.198 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.490      ;
; 1.219 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.512      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.514      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.523      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.239 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.531      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.534      ;
; 1.248 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.540      ;
; 1.249 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.541      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.542      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.543      ;
; 1.266 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.081      ; 1.559      ;
; 1.270 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.562      ;
; 1.298 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.590      ;
; 1.299 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.588      ;
; 1.300 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.589      ;
; 1.302 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.599      ;
; 1.314 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.603      ;
; 1.317 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.606      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01011                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortWEn                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0101        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXStMachCurrState.0110        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TxByteCtrl[2]             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutFullSpeedRate  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                          ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.504 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.795      ;
; 0.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 0.801      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.041      ;
; 0.750 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.041      ;
; 0.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.751 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.752 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.043      ;
; 0.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.055      ;
; 0.767 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.058      ;
; 0.773 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.064      ;
; 1.101 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.101 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.394      ;
; 1.104 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.395      ;
; 1.104 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.395      ;
; 1.107 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.110 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.113 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.404      ;
; 1.116 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.413      ;
; 1.128 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.419      ;
; 1.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.428      ;
; 1.231 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.524      ;
; 1.232 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.232 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.525      ;
; 1.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.526      ;
; 1.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.526      ;
; 1.240 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.533      ;
; 1.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.241 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.243 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.534      ;
; 1.244 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.535      ;
; 1.247 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.540      ;
; 1.247 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.541      ;
; 1.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.541      ;
; 1.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.543      ;
; 1.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.543      ;
; 1.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.544      ;
; 1.256 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.549      ;
; 1.256 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.081      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
; 1.258 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.549      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.381     ; 6.615      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.395     ; 6.601      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 6.619      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 6.619      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.379     ; 6.617      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.381     ; 6.615      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.381     ; 6.615      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.379     ; 6.617      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.379     ; 6.617      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.381     ; 6.615      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 6.605      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 6.605      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 6.619      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 6.619      ;
; 4.503 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.393     ; 6.603      ;
; 4.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.389     ; 6.606      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 6.807      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 6.805      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.195     ; 6.805      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 6.806      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.792      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 6.806      ;
; 4.511 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.792      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.791      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.791      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.791      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.208     ; 6.791      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 6.805      ;
; 4.512 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 6.793      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 6.725      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 6.725      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 6.725      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 6.711      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.268     ; 6.707      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.266     ; 6.709      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 6.711      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 6.725      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.254     ; 6.721      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.254     ; 6.721      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.254     ; 6.721      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.254     ; 6.721      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.252     ; 6.723      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.252     ; 6.723      ;
; 4.536 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.252     ; 6.723      ;
; 4.537 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.262     ; 6.712      ;
; 4.612 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 6.830      ;
; 4.612 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 6.830      ;
; 4.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 6.544      ;
; 4.761 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 6.544      ;
; 4.762 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 6.543      ;
; 4.762 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 6.543      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 6.399      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 6.403      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 6.400      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 6.399      ;
; 5.055 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 6.399      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 6.383      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 6.398      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.403      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.187     ; 6.398      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 6.389      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 6.389      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 6.389      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 6.389      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 6.383      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
; 5.056 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.200     ; 6.385      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                        ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.935 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 5.532      ;
; 5.935 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 5.532      ;
; 5.935 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.174     ; 5.532      ;
; 5.936 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 5.545      ;
; 5.936 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 5.545      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[10]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[10]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.025      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[9]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[11]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[11]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out7_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.447 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.026      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 5.023      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 5.023      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 5.022      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.025      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.025      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.025      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.025      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 5.012      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 5.025      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[31]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[2]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[3]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 5.024      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[8]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[8]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[9]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[9]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[10]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[10]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[11]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[11]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.015      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[12]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[12]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 5.017      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 5.013      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 5.011      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[13]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[14]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[15]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[16]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[17]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[18]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[19]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
; 6.448 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[20]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 5.018      ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 5.233      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 5.233      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.234      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.234      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.234      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.234      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 5.233      ;
; 11.907 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.191     ; 5.233      ;
; 11.908 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.233      ;
; 11.908 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.190     ; 5.233      ;
; 11.909 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.247     ; 5.175      ;
; 11.909 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.247     ; 5.175      ;
; 11.925 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.225     ; 5.181      ;
; 11.926 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.226     ; 5.179      ;
; 12.449 ; sdram_reset_n_reg ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.193     ; 4.819      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.453 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.186     ; 4.822      ;
; 12.463 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.826      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 4.828      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.826      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.826      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.826      ;
; 12.463 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.174     ; 4.823      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.173     ; 4.824      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.174     ; 4.823      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.826      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
; 12.464 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.172     ; 4.825      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.412      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.411      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.411      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.212      ; 4.414      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.413      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.411      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.411      ;
; 3.970 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.411      ;
; 3.971 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.211      ; 4.414      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.209      ; 4.412      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.413      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.413      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.413      ;
; 3.971 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.210      ; 4.413      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.257 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.222      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.216      ; 4.706      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.258 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 4.711      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_busy_reg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.mstr_ack         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack1         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack2         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.700      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.700      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[16]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.700      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|sda_int                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.700      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[7]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.211      ; 4.702      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.209      ; 4.700      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|busy                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|paused_reg                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.223      ; 4.714      ;
; 4.259 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.701      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.699      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 4.712      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.699      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.213      ; 4.705      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 4.712      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 4.712      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.695      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.695      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.695      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.203      ; 4.695      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[2]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[3]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[1]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[0]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[5]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[7]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[6]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[4]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.208      ; 4.700      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.697      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.210      ; 4.702      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.697      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.697      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.697      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 4.711      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.699      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.699      ;
; 4.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.205      ; 4.697      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.697      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.204      ; 4.697      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 4.688      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.700      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.700      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.700      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 4.688      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.689      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.700      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[26]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.689      ;
; 4.261 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 4.700      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.497 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.182      ; 5.911      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.199      ; 5.929      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.915      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.915      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.915      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.915      ;
; 5.498 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.915      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.909      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.925      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.925      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.909      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.909      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.925      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.929      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.925      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.499 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 5.926      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 5.913      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 5.916      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 5.916      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 5.916      ;
; 5.500 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 5.916      ;
; 5.502 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.919      ;
; 5.502 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.919      ;
; 5.502 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.919      ;
; 5.502 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.919      ;
; 5.502 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 5.919      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.503 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 5.915      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.930      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 5.932      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 5.932      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 5.932      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 5.932      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 5.932      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.930      ;
; 5.504 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.194      ; 5.930      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.505 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.198      ; 5.935      ;
; 5.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 6.057      ;
; 5.732 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 6.057      ;
; 5.733 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 6.057      ;
; 5.733 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 6.057      ;
; 5.899 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 6.312      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.519 ; 5.739        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.523 ; 5.743        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.525 ; 5.745        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.525 ; 5.745        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.525 ; 5.745        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.525 ; 5.745        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.525 ; 5.745        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.428 ; 8.648        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.429 ; 8.649        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scanlines_reg                                                                                   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ;
; 8.431 ; 8.651        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg                          ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ;
; 8.432 ; 8.652        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                      ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.433 ; 8.653        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                         ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                 ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                         ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                   ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                          ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                          ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                          ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                      ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                           ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                            ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]                              ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[0]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[10] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[11] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[12] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[13] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[14] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[15] ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[1]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[2]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[3]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[4]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[5]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[6]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[7]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[8]  ;
; 10.115 ; 10.335       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|timeOutCnt[9]  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[1]                                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[2]                                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                    ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                        ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|fifoFull                                                            ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                 ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101                  ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                            ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                            ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync                          ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                     ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]                     ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]                     ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]                     ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                ;
; 10.116 ; 10.336       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                          ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                       ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                            ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                             ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                             ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                             ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                             ;
; 17.014 ; 17.415       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                             ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                       ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                            ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                             ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                             ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                             ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                             ;
; 17.086 ; 17.487       ; 0.401          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                             ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[10]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[11]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[12]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[13]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[14]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[15]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[16]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[17]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[18]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[19]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[20]                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|dac_out                                                                                                                                                                   ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[13]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[14]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[15]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[16]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[17]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[18]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[19]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[20]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[21]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[22]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p1[23]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[12]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[13]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[14]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[15]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[16]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[17]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[18]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[19]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[20]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[21]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[22]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_fwd_p2[23]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[12]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[13]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[14]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[15]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[16]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[17]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[18]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[19]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[20]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[21]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[22]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; hq_dac:dac_right|r_data_lpf_p2[23]                                                                                                                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[1] ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2] ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[0]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[1]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[2]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[3]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[4]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[5]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[6]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audc3_reg[7]                                                                          ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|chan3_output_reg                                                                      ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3|out_reg                                        ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|volume_channel_3_reg[0]                                                               ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|volume_channel_3_reg[1]                                                               ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|volume_channel_3_reg[2]                                                               ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|volume_channel_3_reg[3]                                                               ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[0]                      ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[1]                      ;
; 17.160 ; 17.380       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[2]                      ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.435 ; 17.435       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.484 ; 17.484       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.442 ; 99.744       ; 10.302         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 89.948 ; 100.250      ; 10.302         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.744 ; 99.744       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.762 ; 99.950       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.787 ; 99.787       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.800 ; 99.800       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.829 ; 100.049      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.900 ; 99.900       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.902 ; 99.902       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.925 ; 99.925       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046  ; 3.153  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040  ; 3.147  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038  ; 3.145  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034  ; 3.141  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046  ; 3.153  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032  ; 3.139  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026  ; 3.133  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024  ; 3.131  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014  ; 3.121  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024  ; 3.131  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 12.289 ; 12.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 7.496  ; 7.732  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 12.289 ; 12.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 7.681  ; 7.968  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 11.937 ; 12.214 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.595  ; 3.844  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; 5.864  ; 5.983  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 13.706 ; 14.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 7.933  ; 8.058  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 13.706 ; 14.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 7.917  ; 8.187  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 11.855 ; 12.204 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 4.549  ; 4.747  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; 5.967  ; 6.020  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.339  ; 6.668  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.465  ; 6.740  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.402  ; 4.561  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864  ; 0.974  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.864  ; 0.974  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.030 ; -2.137 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.539 ; -2.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -4.397 ; -4.625 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -5.759 ; -5.982 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.918 ; -5.226 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -5.349 ; -5.586 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.539 ; -2.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; -4.373 ; -4.531 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -3.422 ; -3.600 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -5.343 ; -5.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -4.862 ; -5.112 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -5.205 ; -5.550 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -5.270 ; -5.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.422 ; -3.600 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; -4.471 ; -4.565 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.163 ; -5.469 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.290 ; -5.541 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.329 ; -3.486 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284 ; 2.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293 ; 3.004 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302 ; 3.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389 ; 3.932 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303 ; 3.014 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313 ; 3.024 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289 ; 3.000 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290 ; 3.001 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376 ; 3.919 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388 ; 3.931 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.588 ; 3.277 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.588 ; 3.277 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.588 ; 3.277 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430 ; 3.975 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425 ; 3.970 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356 ; 2.151 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477 ; 3.180 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486 ; 3.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608 ; 3.297 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450 ; 3.995 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.604 ; 3.293 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.594 ; 3.283 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442 ; 3.987 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586 ; 3.275 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596 ; 3.285 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.327 ; 4.762 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.787 ; 4.094 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.327 ; 4.762 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300 ; 3.011 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311 ; 3.022 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.900 ; 7.122 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.424 ; 4.271 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.611 ; 3.413 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.880 ; 7.086 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 4.115 ; 4.230 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.089 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.849 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.605 ; 2.568 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.179 ; 5.520 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.375 ; 2.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.157 ; 5.498 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.068 ; 5.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.317 ; 2.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.307 ; 2.183 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.057 ; 5.343 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.286 ; 2.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.297 ; 2.173 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.287 ; 2.163 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.296 ; 2.172 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.741 ; 2.436 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.731 ; 2.426 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.905 ; 3.206 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.905 ; 3.206 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.423 ; 3.848 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.022 ; 6.249 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.543 ; 3.395 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.748 ; 2.554 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 5.996 ; 6.206 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.227 ; 3.341 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.319 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.083 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.790 ; 1.754 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.364 ; 4.706 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.561 ; 1.505 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.343 ; 4.685 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.251 ; 4.538 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.500 ; 1.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.490 ; 1.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.240 ; 4.527 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.469 ; 1.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.480 ; 1.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.470 ; 1.347 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.479 ; 1.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.831 ; 2.831 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.621 ; 3.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.621 ; 3.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.621 ; 3.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.705 ; 3.705 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.106 ; 4.106 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.494 ; 4.494 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.484 ; 4.484 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.477 ; 4.477 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.330 ; 3.330 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.954 ; 2.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.841 ; 2.841 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.841 ; 2.841 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.831 ; 2.831 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.858 ; 2.858 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.848 ; 2.848 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.858 ; 2.858 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.110 ; 3.726 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 8.735 ; 8.351 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 8.735 ; 8.351 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 1.524 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.253 ; 2.282 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.253 ; 2.282 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.253 ; 2.282 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.333 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.719 ; 2.748 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.091 ; 3.120 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.082 ; 3.111 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.075 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.974 ; 2.003 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.613 ; 1.642 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.505 ; 1.534 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.505 ; 1.534 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.495 ; 1.524 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.521 ; 1.550 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.511 ; 1.540 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.521 ; 1.550 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.130 ; 2.762 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 7.926 ; 7.558 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 7.926 ; 7.558 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.550     ; 2.790     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.287     ; 3.527     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.287     ; 3.527     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.287     ; 3.527     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.375     ; 3.615     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.756     ; 3.996     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.110     ; 4.350     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.113     ; 4.353     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.107     ; 4.347     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.056     ; 3.296     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.704     ; 2.944     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.560     ; 2.800     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.560     ; 2.800     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.550     ; 2.790     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.579     ; 2.819     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.569     ; 2.809     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.579     ; 2.819     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.585     ; 3.969     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 8.116     ; 8.500     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 8.116     ; 8.500     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.456     ; 1.456     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.163     ; 2.163     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.163     ; 2.163     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.163     ; 2.163     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.247     ; 2.247     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.613     ; 2.613     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.953     ; 2.953     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.956     ; 2.956     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.950     ; 2.950     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.942     ; 1.942     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.604     ; 1.604     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.466     ; 1.466     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.466     ; 1.466     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.456     ; 1.456     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.483     ; 1.483     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.473     ; 1.473     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.483     ; 1.483     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.626     ; 2.994     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 7.332     ; 7.700     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 7.332     ; 7.700     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                              ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note                                           ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
; 45.56 MHz  ; 45.56 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 77.17 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                       ; limit due to minimum period restriction (tmin) ;
; 119.4 MHz  ; 119.4 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;                                                ;
; 132.4 MHz  ; 132.4 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 133.24 MHz ; 133.24 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+--------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.061  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.848  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.907  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 12.458 ; 0.000         ;
; FPGA_CLK                                                                       ; 93.521 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.385 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.402 ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 0.402 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
; FPGA_CLK                                                                       ; 0.470 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.070  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.462  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.318 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.566 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.864 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 4.979 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.517  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.431  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.114 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.031 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.426 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.446 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.061 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 4.638      ;
; 1.213 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 4.486      ;
; 1.214 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 4.485      ;
; 1.295 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.403      ;
; 1.340 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.232      ;
; 1.351 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.221      ;
; 1.356 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.123     ; 4.343      ;
; 1.457 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 4.114      ;
; 1.473 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 4.097      ;
; 1.484 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 4.086      ;
; 1.554 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 4.017      ;
; 1.572 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.126      ;
; 1.572 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.126      ;
; 1.573 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.125      ;
; 1.574 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 4.124      ;
; 1.643 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.116     ; 4.063      ;
; 1.644 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.116     ; 4.062      ;
; 1.646 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.116     ; 4.060      ;
; 1.651 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.116     ; 4.055      ;
; 1.654 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.116     ; 4.052      ;
; 1.661 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 3.898      ;
; 1.693 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.139     ; 3.864      ;
; 1.796 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.139     ; 3.761      ;
; 1.808 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.762      ;
; 1.808 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.762      ;
; 1.816 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.742      ;
; 1.819 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.751      ;
; 1.819 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.751      ;
; 1.827 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.731      ;
; 1.926 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.632      ;
; 1.926 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.632      ;
; 1.926 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.632      ;
; 1.926 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.632      ;
; 1.933 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 3.638      ;
; 1.937 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.621      ;
; 1.937 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.621      ;
; 1.937 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.621      ;
; 1.937 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.621      ;
; 1.944 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 3.627      ;
; 1.953 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 3.607      ;
; 1.964 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 3.596      ;
; 2.058 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 3.502      ;
; 2.069 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 3.491      ;
; 2.207 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 3.364      ;
; 2.270 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.438      ;
; 2.270 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 3.438      ;
; 2.340 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.218      ;
; 2.351 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.207      ;
; 2.452 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 3.244      ;
; 2.462 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 3.096      ;
; 2.622 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 2.924      ;
; 2.670 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 2.876      ;
; 2.674 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.139     ; 2.883      ;
; 2.674 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 3.011      ;
; 2.678 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 3.007      ;
; 2.683 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 3.002      ;
; 2.684 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 3.001      ;
; 2.701 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 2.994      ;
; 2.713 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.980      ;
; 2.714 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.979      ;
; 2.715 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.845      ;
; 2.716 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.977      ;
; 2.720 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 2.838      ;
; 2.721 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.972      ;
; 2.724 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 2.969      ;
; 2.732 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.954      ;
; 2.738 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.833      ;
; 2.741 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.945      ;
; 2.742 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.944      ;
; 2.743 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.817      ;
; 2.766 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.805      ;
; 2.774 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 2.912      ;
; 2.779 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.918      ;
; 2.779 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.125     ; 2.918      ;
; 2.837 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 2.848      ;
; 2.943 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 2.629      ;
; 2.962 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 2.733      ;
; 2.972 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.124     ; 2.600      ;
; 2.973 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 2.735      ;
; 2.974 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 2.734      ;
; 2.975 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 2.571      ;
; 3.004 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.150     ; 2.542      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.035 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.661      ;
; 3.073 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.138     ; 2.485      ;
; 3.092 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.604      ;
; 3.092 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.604      ;
; 3.092 ; SDRAM_READ_ENABLE       ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 2.604      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.848 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 8.628      ;
; 2.856 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 8.626      ;
; 2.910 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 8.573      ;
; 3.086 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 8.391      ;
; 3.314 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 8.159      ;
; 3.354 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 8.130      ;
; 3.523 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.961      ;
; 3.573 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 7.910      ;
; 3.588 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.889      ;
; 3.607 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 7.878      ;
; 3.625 ; ram_do_reg[0]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.852      ;
; 3.677 ; ram_do_reg[6]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.800      ;
; 3.693 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.791      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.705 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.771      ;
; 3.706 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.173     ; 7.763      ;
; 3.715 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.750      ;
; 3.715 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.750      ;
; 3.715 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[6]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.750      ;
; 3.715 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.750      ;
; 3.720 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.764      ;
; 3.724 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.743      ;
; 3.724 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.743      ;
; 3.756 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.700      ;
; 3.756 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[10]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.700      ;
; 3.756 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.700      ;
; 3.756 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_address_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.700      ;
; 3.771 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.694      ;
; 3.771 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.694      ;
; 3.771 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.694      ;
; 3.771 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposp3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.694      ;
; 3.778 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.699      ;
; 3.781 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 7.702      ;
; 3.802 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.663      ;
; 3.804 ; ram_do_reg[1]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.673      ;
; 3.819 ; ram_do_reg[2]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 7.664      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.826 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.639      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[6]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[0]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[1]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[2]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[3]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[4]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.838 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp0_reg[5]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.626      ;
; 3.854 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[0]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.610      ;
; 3.854 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[1]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.610      ;
; 3.897 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[6]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.570      ;
; 3.897 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafm_reg[7]                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 7.570      ;
; 3.914 ; ram_do_reg[5]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.570      ;
; 3.935 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp3_reg[5]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.541      ;
; 3.935 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|grafp3_reg[7]                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.166     ; 7.541      ;
; 3.947 ; ram_do_reg[1]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.530      ;
; 3.954 ; ram_do_reg[1]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.523      ;
; 3.958 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[41]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 7.525      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[9] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[8] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.962 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.169     ; 7.511      ;
; 3.967 ; ram_do_reg[0]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 7.517      ;
; 3.967 ; ram_do_reg[0]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.165     ; 7.510      ;
; 3.972 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.492      ;
; 3.972 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.492      ;
; 3.972 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.492      ;
; 3.972 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.492      ;
; 3.973 ; ram_do_reg[0]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 7.512      ;
; 3.984 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.480      ;
; 3.984 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.480      ;
; 3.984 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.480      ;
; 3.984 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.480      ;
; 3.984 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.480      ;
; 3.995 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 7.486      ;
; 3.995 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 7.486      ;
; 3.995 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.161     ; 7.486      ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.907  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 7.286      ;
; 10.163 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 7.030      ;
; 10.241 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.142     ; 6.953      ;
; 10.360 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.121     ; 6.855      ;
; 10.467 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.747      ;
; 10.563 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.651      ;
; 10.622 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.121     ; 6.593      ;
; 10.715 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.499      ;
; 10.724 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.142     ; 6.470      ;
; 10.731 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.462      ;
; 10.774 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.440      ;
; 10.783 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 6.464      ;
; 10.785 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.461      ;
; 10.802 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.412      ;
; 10.806 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.387      ;
; 10.812 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.434      ;
; 10.847 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.121     ; 6.368      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.850 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.137     ; 6.475      ;
; 10.852 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.341      ;
; 10.864 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.142     ; 6.330      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.870 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.138     ; 6.454      ;
; 10.943 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.121     ; 6.272      ;
; 10.948 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 6.299      ;
; 10.971 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.222      ;
; 10.984 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.262      ;
; 11.017 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.176      ;
; 11.028 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.218      ;
; 11.047 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.199      ;
; 11.050 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.196      ;
; 11.054 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 6.193      ;
; 11.073 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.402     ; 5.987      ;
; 11.086 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 5.964      ;
; 11.119 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.127      ;
; 11.148 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.143     ; 6.045      ;
; 11.184 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.402     ; 5.876      ;
; 11.206 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 6.040      ;
; 11.212 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 6.002      ;
; 11.244 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.402     ; 5.816      ;
; 11.253 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.993      ;
; 11.257 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 5.793      ;
; 11.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.984      ;
; 11.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.980      ;
; 11.306 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.142     ; 5.888      ;
; 11.338 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.402     ; 5.722      ;
; 11.342 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.903      ;
; 11.369 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.877      ;
; 11.369 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.878      ;
; 11.401 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 5.649      ;
; 11.411 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.835      ;
; 11.423 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 5.791      ;
; 11.457 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.408     ; 5.597      ;
; 11.461 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.785      ;
; 11.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.412     ; 5.578      ;
; 11.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.774      ;
; 11.492 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.754      ;
; 11.503 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.743      ;
; 11.509 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.737      ;
; 11.523 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.723      ;
; 11.524 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.723      ;
; 11.565 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                          ; scanlines_reg                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.727      ;
; 11.609 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.636      ;
; 11.614 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.632      ;
; 11.620 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.625      ;
; 11.640 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.606      ;
; 11.658 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.588      ;
; 11.741 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.506      ;
; 11.747 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.498      ;
; 11.762 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.485      ;
; 11.767 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.480      ;
; 11.809 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.437      ;
; 11.810 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.437      ;
; 11.811 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.435      ;
; 11.817 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.089     ; 5.430      ;
; 11.826 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.419      ;
; 11.830 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.415      ;
; 11.847 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.399      ;
; 11.860 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.122     ; 5.354      ;
; 11.946 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 5.300      ;
; 12.047 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_value_reg[1]                                                                                       ; scanlines_reg                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.170     ; 5.245      ;
; 12.055 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 5.190      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 12.458 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.322      ;
; 12.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.258      ;
; 12.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.217      ;
; 12.627 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.153      ;
; 12.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.103      ;
; 12.741 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 8.039      ;
; 12.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.966      ;
; 12.830 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.950      ;
; 12.862 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.902      ;
; 12.863 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.901      ;
; 12.864 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.900      ;
; 12.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.902      ;
; 12.914 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.850      ;
; 12.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.849      ;
; 12.916 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.848      ;
; 12.935 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.845      ;
; 13.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.733      ;
; 13.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.732      ;
; 13.033 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.731      ;
; 13.049 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.731      ;
; 13.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.594      ;
; 13.223 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.541      ;
; 13.224 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.540      ;
; 13.225 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.539      ;
; 13.328 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.436      ;
; 13.329 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.435      ;
; 13.330 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.434      ;
; 13.344 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.420      ;
; 13.345 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.419      ;
; 13.346 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.418      ;
; 13.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.372      ;
; 13.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.308      ;
; 13.505 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.259      ;
; 13.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.258      ;
; 13.507 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.257      ;
; 13.569 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.211      ;
; 13.633 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.147      ;
; 13.642 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.122      ;
; 13.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.121      ;
; 13.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 7.120      ;
; 13.660 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.120      ;
; 13.719 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.061      ;
; 13.724 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 7.056      ;
; 13.762 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 7.000      ;
; 13.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.997      ;
; 13.805 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.958      ;
; 13.806 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.957      ;
; 13.807 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.072     ; 6.956      ;
; 13.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.951      ;
; 13.831 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.076     ; 6.802      ;
; 13.866 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.899      ;
; 13.870 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.895      ;
; 13.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.847      ;
; 13.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.839      ;
; 13.957 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.081     ; 6.797      ;
; 13.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.771      ;
; 14.032 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.748      ;
; 14.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.730      ;
; 14.091 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.689      ;
; 14.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.579      ;
; 14.203 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.562      ;
; 14.227 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.538      ;
; 14.259 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.506      ;
; 14.291 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.474      ;
; 14.307 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.458      ;
; 14.332 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.433      ;
; 14.348 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.417      ;
; 14.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.390      ;
; 14.393 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.081     ; 6.361      ;
; 14.400 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.077     ; 6.232      ;
; 14.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.377      ;
; 14.423 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.342      ;
; 14.436 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.077     ; 6.196      ;
; 14.438 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.071     ; 6.326      ;
; 14.441 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.339      ;
; 14.468 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.297      ;
; 14.497 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.268      ;
; 14.498 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.282      ;
; 14.501 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.279      ;
; 14.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.256      ;
; 14.511 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.269      ;
; 14.523 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.061     ; 6.251      ;
; 14.549 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.231      ;
; 14.549 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.216      ;
; 14.565 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.215      ;
; 14.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.061     ; 6.187      ;
; 14.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.082     ; 6.153      ;
; 14.605 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.160      ;
; 14.616 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.149      ;
; 14.622 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.145      ;
; 14.623 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.144      ;
; 14.624 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.068     ; 6.143      ;
; 14.646 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.119      ;
; 14.660 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.120      ;
; 14.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.099      ;
; 14.673 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.107      ;
; 14.674 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.091      ;
; 14.690 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.070     ; 6.075      ;
; 14.700 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.077     ; 5.932      ;
; 14.711 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.055     ; 6.069      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                        ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 93.521  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; -1.396     ; 5.085      ;
; 97.478  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; 1.184      ; 0.959      ;
; 196.789 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.144      ;
; 196.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.105      ;
; 196.872 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.061      ;
; 196.915 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.018      ;
; 196.918 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 3.015      ;
; 196.954 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.979      ;
; 196.957 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.976      ;
; 196.993 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.940      ;
; 196.995 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.938      ;
; 196.998 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.935      ;
; 197.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.903      ;
; 197.041 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.892      ;
; 197.044 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.889      ;
; 197.069 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.864      ;
; 197.080 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.853      ;
; 197.083 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.850      ;
; 197.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.814      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.812      ;
; 197.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.811      ;
; 197.124 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.809      ;
; 197.130 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.803      ;
; 197.156 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.777      ;
; 197.166 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.767      ;
; 197.167 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.766      ;
; 197.170 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.763      ;
; 197.195 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.738      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.728      ;
; 197.206 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.727      ;
; 197.209 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.724      ;
; 197.245 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.688      ;
; 197.247 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.686      ;
; 197.248 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.685      ;
; 197.250 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.683      ;
; 197.253 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.680      ;
; 197.256 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.677      ;
; 197.257 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.676      ;
; 197.282 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.651      ;
; 197.292 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.641      ;
; 197.293 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.640      ;
; 197.293 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.640      ;
; 197.296 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.637      ;
; 197.321 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.612      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.602      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.601      ;
; 197.332 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.601      ;
; 197.335 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.598      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.350 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.074     ; 2.578      ;
; 197.371 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.562      ;
; 197.373 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.560      ;
; 197.374 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.559      ;
; 197.376 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.557      ;
; 197.376 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.557      ;
; 197.379 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.554      ;
; 197.379 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.554      ;
; 197.382 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.551      ;
; 197.383 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.550      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.386 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.076     ; 2.540      ;
; 197.408 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.525      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.515      ;
; 197.419 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.419 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.514      ;
; 197.420 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.513      ;
; 197.422 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.511      ;
; 197.447 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.486      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.476      ;
; 197.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.475      ;
; 197.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.475      ;
; 197.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.474      ;
; 197.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.472      ;
; 197.497 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.436      ;
; 197.499 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.434      ;
; 197.500 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.433      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.431      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.431      ;
; 197.502 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.069     ; 2.431      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.385 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[1]                                                                      ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.038      ;
; 0.395 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[7]                                                                      ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.423      ; 1.048      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_2_dff      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_2_dff                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|empty_dff           ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|empty_dff                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[0]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[0]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audf3_reg[0]                                                                          ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|audf3_reg[0]                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|irqst_reg[6]                                                                          ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|irqst_reg[6]                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|irqst_reg[5]                                                                          ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|irqst_reg[5]                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                             ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                             ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                             ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[373]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[373]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[20]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[44]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[44]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[53]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[21]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[21]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[34]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[34]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[50]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[50]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[49]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[49]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[42]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[26]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[26]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[43]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[43]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[28]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[51]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[51]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[35]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[11]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[11]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[27]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[27]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[12]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[12]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[30]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[30]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[46]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[46]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[372]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[372]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[7]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[7]                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[363]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[363]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[131]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[131]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[370]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[370]                                                                                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_reset_n_reg                                                                                                                                                                          ; sdram_reset_n_reg                                                                                                                                                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                          ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.669      ;
; 0.417 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.684      ;
; 0.457 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.724      ;
; 0.457 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.724      ;
; 0.468 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.735      ;
; 0.469 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.737      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.470 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.738      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.471 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.739      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.472 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.740      ;
; 0.473 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.739      ;
; 0.576 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                 ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.166      ; 0.957      ;
; 0.601 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.084      ; 0.880      ;
; 0.611 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.877      ;
; 0.612 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.877      ;
; 0.614 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.073      ; 0.882      ;
; 0.620 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.887      ;
; 0.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.912      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
; 0.646 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.072      ; 0.913      ;
+-------+-------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[5]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[2]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRCData[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001111                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001110                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010001                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011101                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0000  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.417 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.684      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.472 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.738      ;
; 0.488 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.753      ;
; 0.490 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.755      ;
; 0.559 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.824      ;
; 0.561 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.826      ;
; 0.599 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.865      ;
; 0.615 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.881      ;
; 0.659 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.925      ;
; 0.665 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.930      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.951      ;
; 0.685 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.686 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.953      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.956      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.957      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.702 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.968      ;
; 0.702 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.968      ;
; 0.708 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.975      ;
; 0.709 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.976      ;
; 0.723 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.989      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.010      ;
; 0.752 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.018      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.024      ;
; 0.811 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.076      ;
; 0.813 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.078      ;
; 0.813 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.078      ;
; 0.830 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.095      ;
; 0.871 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.137      ;
; 0.878 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.144      ;
; 0.888 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.154      ;
; 0.891 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.156      ;
; 0.903 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.169      ;
; 0.937 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.203      ;
; 0.941 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.207      ;
; 0.954 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.221      ;
; 0.970 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.235      ;
; 0.994 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.260      ;
; 1.005 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.272      ;
; 1.005 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.272      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.273      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.273      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.274      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.275      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.278      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.278      ;
; 1.020 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.020 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.287      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.290      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.291      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.291      ;
; 1.054 ; sdram_request_complete_reg                                ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.319      ;
; 1.062 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.327      ;
; 1.080 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.346      ;
; 1.092 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.359      ;
; 1.095 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.361      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.367      ;
; 1.102 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.367      ;
; 1.105 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.372      ;
; 1.105 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.372      ;
; 1.125 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.391      ;
; 1.127 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.392      ;
; 1.127 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.394      ;
; 1.127 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.394      ;
; 1.128 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.394      ;
; 1.128 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.395      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.396      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.396      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.400      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.400      ;
; 1.142 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.409      ;
; 1.142 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.409      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.412      ;
; 1.146 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.413      ;
; 1.157 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.075      ; 1.427      ;
; 1.157 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.420      ;
; 1.157 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.420      ;
; 1.171 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.437      ;
; 1.172 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.435      ;
; 1.174 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.437      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                           ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.470 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.736      ;
; 0.471 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.737      ;
; 0.472 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.738      ;
; 0.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.959      ;
; 0.693 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.959      ;
; 0.694 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.960      ;
; 0.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.697 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.964      ;
; 0.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.964      ;
; 0.699 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.965      ;
; 0.700 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.966      ;
; 0.701 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.967      ;
; 0.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.976      ;
; 0.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.980      ;
; 0.724 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.990      ;
; 1.013 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.281      ;
; 1.014 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.280      ;
; 1.014 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.280      ;
; 1.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.281      ;
; 1.015 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.281      ;
; 1.016 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.282      ;
; 1.016 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.282      ;
; 1.016 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.282      ;
; 1.017 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.017 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.017 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.018 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.284      ;
; 1.019 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.019 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.019 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.020 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.021 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.022 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.288      ;
; 1.028 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.296      ;
; 1.029 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.029 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.030 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.031 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.297      ;
; 1.031 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.297      ;
; 1.032 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.298      ;
; 1.032 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.298      ;
; 1.033 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.299      ;
; 1.034 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.300      ;
; 1.034 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.300      ;
; 1.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.301      ;
; 1.048 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.314      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.378      ;
; 1.112 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.378      ;
; 1.113 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.381      ;
; 1.114 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.380      ;
; 1.116 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.382      ;
; 1.116 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.382      ;
; 1.117 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.383      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.384      ;
; 1.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.384      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.385      ;
; 1.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.385      ;
; 1.128 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.394      ;
; 1.134 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.402      ;
; 1.135 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.403      ;
; 1.136 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.402      ;
; 1.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.403      ;
; 1.137 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.403      ;
; 1.138 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.404      ;
; 1.138 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.404      ;
; 1.139 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.407      ;
; 1.139 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.139 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.139 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.140 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.406      ;
; 1.141 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
; 1.141 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.408      ;
; 1.142 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.408      ;
; 1.143 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.409      ;
; 1.143 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.409      ;
; 1.143 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.409      ;
; 1.144 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.410      ;
; 1.149 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.417      ;
; 1.150 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.073      ; 1.418      ;
; 1.151 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.417      ;
; 1.152 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.418      ;
; 1.153 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.419      ;
; 1.153 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.419      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.170     ; 6.276      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 6.274      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 6.274      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 6.274      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 6.275      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.264      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 6.275      ;
; 5.070 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 6.262      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 6.086      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 6.084      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 6.084      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 6.084      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.355     ; 6.073      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 6.086      ;
; 5.077 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.342     ; 6.086      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.345     ; 6.082      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.358     ; 6.069      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.339     ; 6.088      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.345     ; 6.082      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.345     ; 6.082      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.345     ; 6.082      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.352     ; 6.075      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.351     ; 6.076      ;
; 5.078 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.356     ; 6.071      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 6.180      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 6.180      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 6.180      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.235     ; 6.167      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 6.178      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 6.178      ;
; 5.114 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 6.178      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.238     ; 6.163      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 6.165      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.232     ; 6.169      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 6.170      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.219     ; 6.182      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 6.176      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 6.176      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 6.176      ;
; 5.115 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.225     ; 6.176      ;
; 5.183 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 6.288      ;
; 5.183 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.171     ; 6.288      ;
; 5.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.032      ;
; 5.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.032      ;
; 5.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.032      ;
; 5.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 6.032      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.160     ; 5.887      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.164     ; 5.883      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 5.890      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 5.885      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 5.885      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 5.885      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 5.885      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 5.885      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.164     ; 5.883      ;
; 5.595 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.164     ; 5.883      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.178     ; 5.868      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.161     ; 5.885      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.161     ; 5.885      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 5.878      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 5.878      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 5.878      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.168     ; 5.878      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.178     ; 5.868      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
; 5.596 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 5.874      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                          ;
+-------+---------------------------------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                       ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.462 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 5.040      ;
; 6.462 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.140     ; 5.040      ;
; 6.465 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.150     ; 5.027      ;
; 6.465 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.150     ; 5.027      ;
; 6.465 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.150     ; 5.027      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_safe_reg                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.154     ; 4.539      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.154     ; 4.539      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 4.546      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[8]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[9]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[10]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[11]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[12]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[13]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[14]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[15]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.153     ; 4.540      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[7]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[6]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[14]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[11]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[13]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[12]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.rd       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.start    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.wr       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.stop     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.mstr_ack ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.stop     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_data_reg[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|sda_int        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.145     ; 4.548      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 4.546      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.152     ; 4.541      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.152     ; 4.541      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[6]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.545      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[3]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[0]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[0]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.547      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.rd       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.start    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.544      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 4.545      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 4.545      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.148     ; 4.544      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.149     ; 4.543      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 4.536      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 4.533      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 4.533      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 4.533      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 4.533      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.159     ; 4.533      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.146     ; 4.546      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 4.534      ;
; 6.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.147     ; 4.545      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                        ;
+--------+-------------------+------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                        ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 12.318 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.850      ;
; 12.318 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.850      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.169     ; 4.848      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.169     ; 4.848      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.849      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.849      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.849      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.168     ; 4.849      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.169     ; 4.848      ;
; 12.319 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.169     ; 4.848      ;
; 12.340 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.221     ; 4.775      ;
; 12.340 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.221     ; 4.775      ;
; 12.355 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.781      ;
; 12.357 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.200     ; 4.779      ;
; 12.842 ; sdram_reset_n_reg ; scanlines_reg                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.171     ; 4.449      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.164     ; 4.453      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.165     ; 4.452      ;
; 12.855 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.150     ; 4.457      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.148     ; 4.459      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.151     ; 4.456      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
; 12.855 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.152     ; 4.455      ;
+--------+-------------------+------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.566 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.968      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.966      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.188      ; 3.969      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.189      ; 3.970      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.968      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.968      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.968      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.968      ;
; 3.566 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.186      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.184      ; 3.966      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.184      ; 3.966      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.187      ; 3.969      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
; 3.567 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.185      ; 3.967      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.275      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.864 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.268      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.277      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_busy_reg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.277      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 4.277      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 4.268      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.276      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|busy                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.865 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|paused_reg                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.199      ; 4.279      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.265      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.189      ; 4.270      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.267      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.267      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.191      ; 4.272      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.267      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.866 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 4.277      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.254      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.254      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 4.261      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 4.261      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 4.261      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.mstr_ack         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack1         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.slv_ack2         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.179      ; 4.261      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.254      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[2]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[3]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[1]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[0]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[5]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[7]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[6]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[4]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.184      ; 4.266      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|sda_int                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 4.268      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[7]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 4.269      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.181      ; 4.263      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.265      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 4.267      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
; 3.867 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.182      ; 4.264      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.357      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.372      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.360      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.360      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.360      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.360      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.979 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.175      ; 5.369      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.368      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.368      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.361      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.361      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.361      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.361      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.162      ; 5.357      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.368      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.178      ; 5.373      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.368      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 5.359      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 5.359      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 5.359      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 5.359      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.164      ; 5.359      ;
; 4.980 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.166      ; 5.361      ;
; 4.981 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 5.352      ;
; 4.981 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 5.352      ;
; 4.981 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 5.352      ;
; 4.981 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.160      ; 5.356      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.982 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 5.373      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 5.369      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.371      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.371      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.371      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.371      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 5.371      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 5.369      ;
; 4.983 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.171      ; 5.369      ;
; 5.194 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 5.484      ;
; 5.194 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 5.484      ;
; 5.194 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 5.484      ;
; 5.194 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 5.484      ;
; 5.327 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.163      ; 5.705      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.517 ; 5.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                               ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                          ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                                      ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_in_reg                          ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ;
; 8.431 ; 8.647        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scanlines_reg                                                                                   ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.432 ; 8.648        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                     ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq                       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                          ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[0] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[0] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[1] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[2] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[3] ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|sampleCnt[4] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[1]                              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[2]                              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoEmpty                                                         ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|fifoREnDelayed                                                    ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[4]                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[5]                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[6]                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg[0]                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]              ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[1]           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[2]           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn                     ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                      ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00011                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00101                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00110                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01000                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01001                       ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                     ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                               ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 17.031 ; 17.413       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4] ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[10]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[11]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[12]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[13]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[14]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[15]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[16]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[17]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[18]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[19]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[20]      ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[5]       ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[6]       ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[7]       ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[8]       ;
; 17.113 ; 17.495       ; 0.382          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|pokey_mixer:shared_pokey_mixer|yadj_reg[9]       ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_im                                                                                                    ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_neq_branch                                                                                            ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_pop_pc_rel                                                                                            ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_sub                                                                                                   ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_im                                                                                                ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_neq_branch                                                                                        ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_pop_pc_rel                                                                                        ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[1].dec_sub                                                                                               ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[2].dec_im                                                                                                ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns[3].dec_im                                                                                                ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[13]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[15]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[3]                                             ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[11]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[13]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[16]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[17]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[18]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[19]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[26]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[27]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|DATA_WRITE_reg[30]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[0][0]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[0][1]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[0][2]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[1][0]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[1][1]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_current_reg[1][2]                                            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_reg[0]                                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_reg[1]                                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|an_reg[2]                                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|chactl_reg[1]                                                   ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[0]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[1]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[2]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[3]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[4]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[5]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[6]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|colour_clock_shift_reg[7]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[0]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[11]                                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[16]                                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[1]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[20]                                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[21]                                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[2]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[3]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[4]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|delay_display_shift_reg[6]                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|descenders_reg                                                  ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_speed_reg[0]                                                ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_blank_reg                                           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_final_row_reg[2]                                    ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_final_row_reg[3]                                    ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_type_reg[0]                                         ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_type_reg[1]                                         ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|instruction_type_reg[2]                                         ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|map_background_reg                                              ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|multi_colour_character_reg                                      ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|penh_reg[2]                                                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|playfield_display_active_reg                                    ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|playfield_dma_end_reg[10]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|playfield_dma_end_reg[11]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|playfield_dma_end_reg[12]                                       ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|playfield_dma_end_reg[13]                                       ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.437 ; 17.437       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.482 ; 17.482       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.446 ; 99.546       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 90.341 ; 100.441      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.546 ; 99.546       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 99.736 ; 99.736       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.744 ; 99.744       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.756 ; 99.940       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.841 ; 100.057      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.889 ; 99.889       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.914 ; 99.914       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
+--------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654  ; 2.761  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.625  ; 2.732  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.625  ; 2.732  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.625  ; 2.732  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648  ; 2.755  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651  ; 2.758  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649  ; 2.756  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645  ; 2.752  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654  ; 2.761  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642  ; 2.749  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648  ; 2.755  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.648  ; 2.755  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.648  ; 2.755  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.638  ; 2.745  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637  ; 2.744  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627  ; 2.734  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637  ; 2.744  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 11.044 ; 11.645 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 6.608  ; 7.047  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 11.044 ; 11.645 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 6.780  ; 7.279  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 10.807 ; 11.258 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.128  ; 3.447  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; 5.267  ; 5.359  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 12.386 ; 12.971 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 7.005  ; 7.335  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 12.386 ; 12.971 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 6.985  ; 7.453  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 10.632 ; 11.293 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.985  ; 4.299  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; 5.398  ; 5.376  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.568  ; 5.752  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.681  ; 5.834  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.860  ; 4.120  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.728  ; 0.838  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.728  ; 0.838  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.753 ; -1.861 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.192 ; -2.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.853 ; -4.229 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -5.064 ; -5.433 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -4.327 ; -4.828 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -4.718 ; -5.159 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.192 ; -2.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; -3.926 ; -4.067 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.979 ; -3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -4.723 ; -5.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -4.293 ; -4.695 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.577 ; -5.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -4.629 ; -5.249 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.979 ; -3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; -4.053 ; -4.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.527 ; -4.699 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.639 ; -4.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.910 ; -3.163 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.321 ; 4.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.812 ; 4.241 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.321 ; 4.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.083 ; 7.175 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.589 ; 4.326 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.784 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.998 ; 7.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 4.118 ; 4.363 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.874 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.864 ; 2.611 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.035 ; 3.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.035 ; 3.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.524 ; 4.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.304 ; 6.406 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.806 ; 3.553 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.019 ; 2.736 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.215 ; 6.364 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.336 ; 3.576 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.700 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.434 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.089 ; 2.060 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.664 ; 5.013 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.861 ; 1.812 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.643 ; 4.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.547 ; 4.841 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.796 ; 1.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.786 ; 1.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.536 ; 4.830 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.765 ; 1.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.776 ; 1.660 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.775 ; 1.659 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.660 ; 2.660 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.407 ; 3.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.407 ; 3.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.407 ; 3.407 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.482 ; 3.482 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.860 ; 3.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.232 ; 4.232 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.211 ; 4.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.206 ; 4.206 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.113 ; 3.113 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.758 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.670 ; 2.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.670 ; 2.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.660 ; 2.660 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.685 ; 2.685 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.675 ; 2.675 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.685 ; 2.685 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.218 ; 3.842 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 8.553 ; 8.177 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 8.553 ; 8.177 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.628 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.346 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.346 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.346 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.418 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.781 ; 2.781 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.138 ; 3.138 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.118 ; 3.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.113 ; 3.113 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.064 ; 2.064 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.723 ; 1.723 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.638 ; 1.638 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.638 ; 1.638 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.628 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.652 ; 1.652 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.642 ; 1.642 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.652 ; 1.652 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.340 ; 2.979 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 7.815 ; 7.454 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 7.815 ; 7.454 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.490     ; 2.561     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.164     ; 3.235     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.164     ; 3.235     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.164     ; 3.235     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.255     ; 3.326     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.606     ; 3.677     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.924     ; 3.995     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.937     ; 4.008     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.933     ; 4.004     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.966     ; 3.037     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.643     ; 2.714     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.500     ; 2.571     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.500     ; 2.571     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.490     ; 2.561     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.515     ; 2.586     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.505     ; 2.576     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.515     ; 2.586     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.588     ; 3.964     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 7.598     ; 7.974     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 7.598     ; 7.974     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.534     ; 1.670     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.181     ; 2.317     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.181     ; 2.317     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.181     ; 2.317     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.268     ; 2.404     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.605     ; 2.741     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.910     ; 3.046     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.923     ; 3.059     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.919     ; 3.055     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.991     ; 2.127     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.681     ; 1.817     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.544     ; 1.680     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.544     ; 1.680     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.534     ; 1.670     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.557     ; 1.693     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.547     ; 1.683     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.557     ; 1.693     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.735     ; 3.096     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.899     ; 7.260     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 6.899     ; 7.260     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                      ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.525  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.447  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 13.955 ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 16.941 ; 0.000         ;
; FPGA_CLK                                                                       ; 96.738 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.149 ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 0.182 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.187 ; 0.000         ;
; FPGA_CLK                                                                       ; 0.193 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                   ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 8.154  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.994  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 14.867 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.795 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.991 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.562 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.605  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.476  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10.165 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.206 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.437 ; 0.000         ;
; FPGA_CLK                                                                       ; 89.518 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node               ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.525 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 2.163      ;
; 3.565 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 2.068      ;
; 3.592 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 2.096      ;
; 3.595 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 2.093      ;
; 3.605 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 2.082      ;
; 3.606 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 2.027      ;
; 3.682 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.119     ; 2.006      ;
; 3.698 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.933      ;
; 3.727 ; SDRAM_ADDR[13]          ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 1.896      ;
; 3.739 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.948      ;
; 3.739 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.892      ;
; 3.743 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.944      ;
; 3.744 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.943      ;
; 3.745 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.120     ; 1.942      ;
; 3.756 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.876      ;
; 3.756 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.876      ;
; 3.786 ; SDRAM_ADDR[12]          ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 1.837      ;
; 3.789 ; SDRAM_ADDR[22]          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 1.836      ;
; 3.795 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.898      ;
; 3.801 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.892      ;
; 3.809 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.884      ;
; 3.811 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.882      ;
; 3.815 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.878      ;
; 3.857 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.767      ;
; 3.860 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.770      ;
; 3.860 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.770      ;
; 3.898 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.726      ;
; 3.901 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.729      ;
; 3.901 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.130     ; 1.729      ;
; 3.913 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.711      ;
; 3.913 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.711      ;
; 3.913 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.711      ;
; 3.913 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.711      ;
; 3.943 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.689      ;
; 3.954 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.670      ;
; 3.954 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.670      ;
; 3.954 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.670      ;
; 3.954 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.670      ;
; 3.984 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.648      ;
; 3.991 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.134     ; 1.635      ;
; 4.026 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.134     ; 1.600      ;
; 4.032 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.134     ; 1.594      ;
; 4.042 ; SDRAM_ADDR[21]          ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.590      ;
; 4.067 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.134     ; 1.559      ;
; 4.117 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.576      ;
; 4.118 ; SDRAM_WRITE_ENABLE      ; ram_di_reg[14]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.575      ;
; 4.126 ; SDRAM_ADDR[17]          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 1.499      ;
; 4.155 ; SDRAM_READ_ENABLE       ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.469      ;
; 4.188 ; SDRAM_ADDR[2]           ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 1.430      ;
; 4.196 ; SDRAM_WRITE_ENABLE      ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.428      ;
; 4.220 ; SDRAM_ADDR[1]           ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 1.398      ;
; 4.223 ; SDRAM_READ_ENABLE       ; ram_do_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.462      ;
; 4.267 ; SDRAM_ADDR[15]          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.137     ; 1.356      ;
; 4.273 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[11]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.407      ;
; 4.276 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.404      ;
; 4.284 ; SDRAM_ADDR[6]           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.135     ; 1.341      ;
; 4.286 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.394      ;
; 4.292 ; SDRAM_ADDR[19]          ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.339      ;
; 4.293 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.387      ;
; 4.298 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.383      ;
; 4.300 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.381      ;
; 4.302 ; SDRAM_ADDR[16]          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 1.325      ;
; 4.308 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.373      ;
; 4.316 ; SDRAM_ADDR[8]           ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.129     ; 1.315      ;
; 4.319 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.367      ;
; 4.323 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[5]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.363      ;
; 4.323 ; SDRAM_ADDR[5]           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.133     ; 1.304      ;
; 4.324 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.126     ; 1.357      ;
; 4.329 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[13]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.357      ;
; 4.337 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[15]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.349      ;
; 4.339 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.347      ;
; 4.343 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[7]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.343      ;
; 4.346 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[1]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.347      ;
; 4.346 ; SDRAM_WRITE_ENABLE      ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.114     ; 1.347      ;
; 4.355 ; SDRAM_ADDR[20]          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.278      ;
; 4.367 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.313      ;
; 4.380 ; SDRAM_ADDR[9]           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.127     ; 1.253      ;
; 4.383 ; SDRAM_READ_ENABLE       ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.303      ;
; 4.383 ; SDRAM_READ_ENABLE       ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.303      ;
; 4.390 ; SDRAM_ADDR[0]           ; ram_bena_reg[0]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.296      ;
; 4.412 ; SDRAM_ADDR[18]          ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.136     ; 1.212      ;
; 4.416 ; SDRAM_ADDR[14]          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 1.202      ;
; 4.439 ; SDRAM_ADDR[3]           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.142     ; 1.179      ;
; 4.460 ; SDRAM_WIDTH_8BIT_ACCESS ; ram_do_reg[20]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.128     ; 1.219      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[25]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[23]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.480 ; SDRAM_READ_ENABLE       ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.122     ; 1.205      ;
; 4.514 ; SDRAM_READ_ENABLE       ; ram_do_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.172      ;
; 4.514 ; SDRAM_READ_ENABLE       ; ram_do_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.820        ; -0.121     ; 1.172      ;
+-------+-------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                          ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.447 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 4.094      ;
; 7.473 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 4.062      ;
; 7.573 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.968      ;
; 7.657 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.878      ;
; 7.683 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.854      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.792 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum2_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.742      ;
; 7.793 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.750      ;
; 7.814 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.729      ;
; 7.821 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.713      ;
; 7.821 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.713      ;
; 7.821 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[6]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.713      ;
; 7.821 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.713      ;
; 7.824 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 3.718      ;
; 7.836 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.699      ;
; 7.836 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.699      ;
; 7.836 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.699      ;
; 7.836 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hposp3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.699      ;
; 7.842 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.701      ;
; 7.844 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.691      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm2_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.872 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm1_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.662      ;
; 7.873 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.661      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[9] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[8] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[7] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[6] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[5] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.896 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum2_reg[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.090     ; 3.641      ;
; 7.899 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.635      ;
; 7.899 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.635      ;
; 7.899 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.635      ;
; 7.899 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colbk_snap_reg[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.635      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[18] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[19] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[20] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[17] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[16] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.911 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_right|accum_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.628      ;
; 7.913 ; ram_do_reg[7]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[27]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.628      ;
; 7.915 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.618      ;
; 7.915 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.618      ;
; 7.915 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.618      ;
; 7.915 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.618      ;
; 7.915 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpm3_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.618      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|pokey_mixer_mux:pokey_mixer|simple_low_pass_filter:filter_left|accum_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 3.611      ;
; 7.922 ; ram_do_reg[4]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.084     ; 3.621      ;
; 7.934 ; ram_do_reg[6]              ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 3.601      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf0_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf1_snap_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf0_snap_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf1_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf0_snap_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf1_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf0_snap_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf1_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.939 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|colpf0_snap_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.592      ;
; 7.943 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[3]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.588      ;
; 7.943 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[2]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.588      ;
; 7.943 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[1]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.588      ;
; 7.943 ; sdram_request_complete_reg ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|prior_snap_reg[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.588      ;
+-------+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                ; To Node                                                                                                                                                                       ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 13.955 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 3.361      ;
; 14.086 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 3.230      ;
; 14.161 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 3.155      ;
; 14.216 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 3.115      ;
; 14.224 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 3.108      ;
; 14.255 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 3.077      ;
; 14.304 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 3.027      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.331 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.045      ;
; 14.334 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 3.013      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.340 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|hsync_reg                                                             ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.071     ; 3.036      ;
; 14.353 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.963      ;
; 14.354 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.962      ;
; 14.355 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.976      ;
; 14.358 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.958      ;
; 14.378 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.968      ;
; 14.385 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.961      ;
; 14.392 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.940      ;
; 14.406 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.910      ;
; 14.418 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.898      ;
; 14.429 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.903      ;
; 14.442 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.905      ;
; 14.443 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.888      ;
; 14.461 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.886      ;
; 14.464 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.852      ;
; 14.495 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.821      ;
; 14.500 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.845      ;
; 14.504 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.828      ;
; 14.512 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.835      ;
; 14.521 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.825      ;
; 14.524 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.822      ;
; 14.571 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.760      ;
; 14.575 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.771      ;
; 14.578 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.767      ;
; 14.581 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.765      ;
; 14.587 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.729      ;
; 14.621 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 2.609      ;
; 14.625 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.721      ;
; 14.626 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.211     ; 2.610      ;
; 14.628 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.718      ;
; 14.633 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.713      ;
; 14.638 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.069     ; 2.693      ;
; 14.645 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.701      ;
; 14.650 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.084     ; 2.666      ;
; 14.655 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.690      ;
; 14.684 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.211     ; 2.552      ;
; 14.687 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|key_event_reg                                                                                          ; scanlines_reg                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.091     ; 2.669      ;
; 14.695 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.650      ;
; 14.703 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.643      ;
; 14.703 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.643      ;
; 14.709 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.637      ;
; 14.713 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 2.517      ;
; 14.718 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.211     ; 2.518      ;
; 14.742 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.604      ;
; 14.743 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.603      ;
; 14.744 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.602      ;
; 14.758 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.588      ;
; 14.759 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.588      ;
; 14.760 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.585      ;
; 14.776 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.569      ;
; 14.777 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.211     ; 2.459      ;
; 14.780 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 2.450      ;
; 14.784 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.563      ;
; 14.814 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.214     ; 2.419      ;
; 14.816 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.217     ; 2.414      ;
; 14.833 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.514      ;
; 14.833 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.512      ;
; 14.834 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.512      ;
; 14.840 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.506      ;
; 14.863 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.483      ;
; 14.863 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.482      ;
; 14.865 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.480      ;
; 14.872 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|COLOUR_REG[6]                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.102      ; 2.699      ;
; 14.875 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.471      ;
; 14.884 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.462      ;
; 14.887 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|gtia:gtia1|COLOUR_REG[6]                                                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; 0.104      ; 2.686      ;
; 14.895 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.055     ; 2.450      ;
; 14.896 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.068     ; 2.436      ;
; 14.897 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.053     ; 2.450      ;
; 14.907 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.439      ;
; 14.911 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.054     ; 2.435      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                      ; To Node                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 16.941 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.854      ;
; 16.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.845      ;
; 16.981 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.814      ;
; 16.990 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.805      ;
; 17.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.756      ;
; 17.048 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.747      ;
; 17.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.686      ;
; 17.114 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.681      ;
; 17.118 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.677      ;
; 17.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.638      ;
; 17.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.637      ;
; 17.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.637      ;
; 17.154 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.641      ;
; 17.167 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.618      ;
; 17.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.617      ;
; 17.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.617      ;
; 17.209 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.576      ;
; 17.210 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.575      ;
; 17.210 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.575      ;
; 17.212 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.583      ;
; 17.282 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.513      ;
; 17.299 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.484      ;
; 17.305 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.480      ;
; 17.306 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.479      ;
; 17.306 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.479      ;
; 17.308 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.475      ;
; 17.361 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.424      ;
; 17.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.423      ;
; 17.362 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.423      ;
; 17.365 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer3[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.047     ; 3.361      ;
; 17.378 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.407      ;
; 17.379 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.406      ;
; 17.379 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.406      ;
; 17.470 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.315      ;
; 17.471 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.314      ;
; 17.471 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.314      ;
; 17.472 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 3.311      ;
; 17.474 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.321      ;
; 17.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.312      ;
; 17.511 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.284      ;
; 17.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.275      ;
; 17.546 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.249      ;
; 17.549 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.236      ;
; 17.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.235      ;
; 17.550 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.235      ;
; 17.555 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.240      ;
; 17.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.222      ;
; 17.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.221      ;
; 17.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.036     ; 3.221      ;
; 17.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.198      ;
; 17.597 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.188      ;
; 17.607 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.178      ;
; 17.613 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.166      ;
; 17.625 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.160      ;
; 17.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.148      ;
; 17.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.136      ;
; 17.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.111      ;
; 17.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.084      ;
; 17.719 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 3.076      ;
; 17.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.040      ;
; 17.751 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.974      ;
; 17.772 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.013      ;
; 17.775 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[3]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.041     ; 3.004      ;
; 17.780 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 3.005      ;
; 17.799 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.986      ;
; 17.801 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.984      ;
; 17.818 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.967      ;
; 17.820 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.975      ;
; 17.823 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.972      ;
; 17.832 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.893      ;
; 17.833 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 2.957      ;
; 17.841 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.944      ;
; 17.842 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.030     ; 2.948      ;
; 17.842 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.943      ;
; 17.847 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.948      ;
; 17.847 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.938      ;
; 17.855 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[2]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.040     ; 2.925      ;
; 17.860 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.935      ;
; 17.863 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.932      ;
; 17.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.908      ;
; 17.887 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.908      ;
; 17.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.836      ;
; 17.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.829      ;
; 17.896 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[7]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.899      ;
; 17.910 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.875      ;
; 17.915 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 2.868      ;
; 17.918 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.877      ;
; 17.921 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.874      ;
; 17.937 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.848      ;
; 17.943 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 2.840      ;
; 17.944 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.0101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOut[4]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.038     ; 2.838      ;
; 17.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.850      ;
; 17.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.000 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.834      ;
; 17.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.823      ;
; 17.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.822      ;
; 17.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXDataByteCnt[3]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.033     ; 2.822      ;
; 17.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|buffer2[2]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.754      ;
; 17.985 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.048     ; 2.740      ;
; 17.988 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.025     ; 2.807      ;
; 17.989 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.035     ; 2.796      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                        ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 96.738  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; -0.964     ; 2.285      ;
; 99.316  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK     ; FPGA_CLK    ; 100.000      ; 0.862      ; 0.415      ;
; 198.373 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.581      ;
; 198.377 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.577      ;
; 198.441 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.513      ;
; 198.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.510      ;
; 198.445 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.509      ;
; 198.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.506      ;
; 198.455 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.499      ;
; 198.491 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.463      ;
; 198.503 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.451      ;
; 198.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.447      ;
; 198.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.445      ;
; 198.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.442      ;
; 198.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.441      ;
; 198.516 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.438      ;
; 198.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.431      ;
; 198.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.430      ;
; 198.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.395      ;
; 198.560 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.394      ;
; 198.571 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.383      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.379      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.378      ;
; 198.577 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.377      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.374      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.374      ;
; 198.581 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.373      ;
; 198.584 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.370      ;
; 198.591 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.363      ;
; 198.592 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.362      ;
; 198.593 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.361      ;
; 198.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.327      ;
; 198.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.326      ;
; 198.628 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.326      ;
; 198.639 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.315      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.311      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.310      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.309      ;
; 198.645 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.309      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.306      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.306      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.305      ;
; 198.649 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.305      ;
; 198.652 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.302      ;
; 198.659 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.295      ;
; 198.660 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.294      ;
; 198.660 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.294      ;
; 198.661 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.293      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.259      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.258      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.258      ;
; 198.698 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.256      ;
; 198.707 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.247      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.243      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.242      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.241      ;
; 198.713 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.241      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.240      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.238      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.238      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.237      ;
; 198.717 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.237      ;
; 198.718 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.236      ;
; 198.720 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.234      ;
; 198.727 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.227      ;
; 198.728 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.226      ;
; 198.728 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.226      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.225      ;
; 198.729 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.225      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.039     ; 1.186      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.191      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.190      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.190      ;
; 198.765 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.189      ;
; 198.766 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.188      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.772 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.042     ; 1.173      ;
; 198.775 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK     ; FPGA_CLK    ; 200.000      ; -0.033     ; 1.179      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                  ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.149 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[1]                                                                      ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.473      ;
; 0.149 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|dma_cache_reg[7]                                                                      ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.473      ;
; 0.156 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                          ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.481      ;
; 0.157 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                                                         ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.481      ;
; 0.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.481      ;
; 0.161 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[5]                                 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.486      ;
; 0.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.486      ;
; 0.165 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]                                 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.490      ;
; 0.166 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                          ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.491      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.495      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.499      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.499      ;
; 0.179 ; ram_do_reg[31]                                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.381      ;
; 0.179 ; ram_do_reg[21]                                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 0.381      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[1]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[29]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[3]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[6]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[36]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[45]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[33]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[4]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[5]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[37]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[22]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[120]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[90]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                             ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[9]                                                                                                                                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                            ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[10]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                           ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[118]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|assert_data                                                                                                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[6]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[3]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[0]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[4]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                                  ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[2]                                                                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_reset_n_reg                                                                                                                                                                          ; sdram_reset_n_reg                                                                                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                              ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[1]                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                              ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[2]                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                              ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|idle_reg[3]                                                                                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[0]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[2]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[1]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                          ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|bitcount_reg[3]                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                     ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_extended_reg                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                        ; ps2_to_atari5200:keyboard_map1|ps2_keyboard:\gen_ps2_on:keyboard1|pending_keyup_reg                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                      ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|sclk                                                                                                                                                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[14]                                                                  ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|address_decoder:mmu1|ADDR_reg[14]                                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_2_dff      ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|usedw_is_2_dff                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|empty_dff           ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|empty_dff                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                                                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[7]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[6]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[5]     ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|low_addressa[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                           ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.182 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.504      ;
; 0.183 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.218      ; 0.505      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[1]                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferCnt[2]                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.00                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|HCTxGnt                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|muxSOFNotHC                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[0]                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFSent                                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1111                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[0]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[1]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[2]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXSameBitCount[3]                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[6]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[5]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[4]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[3]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[2]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[1]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[0]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                                                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketPID[1]                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00010                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01010                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|fifoReadEn                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01101                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10000                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.10101                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[2]                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortCntl[0]                                                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortCntl[0]                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110010                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110101                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110110                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|USBWireReq                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|USBWireReq                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.10                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|CurrState_txWireArb.11                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|USBTxWireArbiter:u_USBTxWireArbiter|SIETxGnt                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|rstCRC                                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CRC5_8Bit                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|loopEnd[0]                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[1]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[2]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|i[3]                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101100                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100100                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011000                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101010                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100000                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                              ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.314      ;
; 0.212 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.332      ;
; 0.218 ; sdram_request_complete_reg                                ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.337      ;
; 0.250 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.370      ;
; 0.254 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.373      ;
; 0.254 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
; 0.263 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.382      ;
; 0.284 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.289 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.408      ;
; 0.291 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.411      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.297 ; seq_reg[6]                                                ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.416      ;
; 0.298 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.313 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.433      ;
; 0.326 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.445      ;
; 0.329 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.449      ;
; 0.331 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.451      ;
; 0.352 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.471      ;
; 0.353 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.472      ;
; 0.357 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.477      ;
; 0.359 ; seq_reg[10]                                               ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.478      ;
; 0.362 ; seq_reg[5]                                                ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.481      ;
; 0.364 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.484      ;
; 0.365 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.484      ;
; 0.367 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.487      ;
; 0.374 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.494      ;
; 0.395 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.514      ;
; 0.410 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.530      ;
; 0.414 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.533      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.539      ;
; 0.428 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.547      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.449 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.569      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.576      ;
; 0.458 ; sdram_request_complete_reg                                ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.577      ;
; 0.474 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.594      ;
; 0.478 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.598      ;
; 0.491 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.610      ;
; 0.492 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.611      ;
; 0.493 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.613      ;
; 0.495 ; seq_reg[0]                                                ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.614      ;
; 0.497 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.616      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.513 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.632      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.530 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.653      ;
; 0.533 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.039      ; 0.656      ;
; 0.533 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.650      ;
; 0.533 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.650      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                       ; To Node                                                                                                                                                                        ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                         ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                           ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; scanlines_reg                                                                                   ; scanlines_reg                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.307      ;
; 0.192 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.312      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[87]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; half_scandouble_enable_reg                                                                      ; half_scandouble_enable_reg                                                                                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[78]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.200 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_odd_reg                                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.320      ;
; 0.202 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vga_hsync_reg                                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.322      ;
; 0.205 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.325      ;
; 0.219 ; ps2_to_atari5200:keyboard_map1|ps2_keys_reg[17]                                                 ; scanlines_reg                                                                                                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.092      ; 0.415      ;
; 0.252 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.045      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.218      ; 0.583      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[88]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.383      ;
; 0.263 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.382      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
+-------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                           ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                       ; To Node                                                                         ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.193 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.314      ;
; 0.206 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.325      ;
; 0.297 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.417      ;
; 0.297 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.417      ;
; 0.298 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.298 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.417      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.418      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.300 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.419      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.420      ;
; 0.305 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.425      ;
; 0.309 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.428      ;
; 0.311 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.431      ;
; 0.446 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.566      ;
; 0.446 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.566      ;
; 0.447 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.447 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.566      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.568      ;
; 0.448 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.567      ;
; 0.449 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.449 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.568      ;
; 0.450 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.569      ;
; 0.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.576      ;
; 0.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.574      ;
; 0.456 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.579      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.577      ;
; 0.458 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.578      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.578      ;
; 0.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.579      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.460 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.580      ;
; 0.461 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.581      ;
; 0.462 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.581      ;
; 0.467 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.586      ;
; 0.470 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.589      ;
; 0.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.629      ;
; 0.509 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.629      ;
; 0.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.632      ;
; 0.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.510 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.629      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.631      ;
; 0.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.630      ;
; 0.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.631      ;
; 0.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.632      ;
; 0.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.513 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.632      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.634      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.634      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.634      ;
; 0.514 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.633      ;
; 0.515 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.634      ;
; 0.516 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.635      ;
; 0.517 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.637      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.640      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.642      ;
; 0.520 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.642      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.645      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.643      ;
; 0.523 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.038      ; 0.645      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.643      ;
; 0.524 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.644      ;
; 0.525 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.035      ; 0.644      ;
; 0.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.646      ;
; 0.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.646      ;
; 0.526 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK     ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.646      ;
+-------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 8.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 3.306      ;
; 8.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 3.306      ;
; 8.154 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 3.306      ;
; 8.155 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.132     ; 3.293      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.248      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.248      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.248      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.129     ; 3.295      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 3.290      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.128     ; 3.296      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 3.304      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.124     ; 3.300      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.124     ; 3.300      ;
; 8.156 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.124     ; 3.300      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.235      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.128     ; 3.295      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 3.297      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 3.297      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 3.297      ;
; 8.157 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 3.297      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 3.232      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.246      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.178     ; 3.242      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.178     ; 3.242      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.178     ; 3.242      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 3.237      ;
; 8.158 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 3.238      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.239      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.239      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.239      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 3.239      ;
; 8.159 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 3.237      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 3.316      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.098     ; 3.316      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.166 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 3.310      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 3.318      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.097     ; 3.316      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.096     ; 3.317      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 3.311      ;
; 8.167 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.096     ; 3.317      ;
; 8.202 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.089     ; 3.336      ;
; 8.202 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.089     ; 3.336      ;
; 8.284 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 3.194      ;
; 8.284 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 3.194      ;
; 8.284 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 3.194      ;
; 8.284 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 3.194      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.391 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.156      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.152      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.082     ; 3.153      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.082     ; 3.153      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.082     ; 3.153      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.082     ; 3.153      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.082     ; 3.153      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.152      ;
; 8.392 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.152      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.150      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.150      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 3.143      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.153      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.153      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.153      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.083     ; 3.150      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.080     ; 3.153      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
; 8.394 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.079     ; 3.154      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                         ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 8.994 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.072     ; 2.561      ;
; 8.994 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.072     ; 2.561      ;
; 8.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.552      ;
; 8.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.552      ;
; 8.996 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.552      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.078     ; 2.329      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|bit_cnt[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.078     ; 2.329      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.332      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.332      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.332      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.330      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.332      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.330      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.077     ; 2.330      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.075     ; 2.332      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[2]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[3]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[3]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[4]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[5]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[6]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[7]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[8]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[8]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[9]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[10]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[11]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[12]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[12]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[13]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[14]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[15]                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.079     ; 2.328      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 2.325      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 2.325      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[12]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[26]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[30]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[13]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[14]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[15]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[20]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[21]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[22]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[23]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[24]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[25]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[26]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[27]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[28]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[29]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[30]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_threshold_reg[31]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[31]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.081     ; 2.326      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.080     ; 2.327      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[8]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
; 9.220 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.076     ; 2.331      ;
+-------+---------------------------------------+------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 14.867 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.126     ; 2.407      ;
; 14.867 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.126     ; 2.407      ;
; 14.877 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.111     ; 2.412      ;
; 14.878 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|b_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.110     ; 2.412      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|vsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.097     ; 2.412      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.096     ; 2.413      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.096     ; 2.413      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.096     ; 2.413      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|g_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.096     ; 2.413      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[6]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.095     ; 2.414      ;
; 14.891 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[7]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.095     ; 2.414      ;
; 14.892 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|hsync_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.097     ; 2.411      ;
; 14.892 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[4]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.097     ; 2.411      ;
; 14.892 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|r_reg[5]                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.097     ; 2.411      ;
; 15.116 ; sdram_reset_n_reg ; scanlines_reg                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.090     ; 2.241      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.120 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.087     ; 2.240      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.242      ;
; 15.125 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.078     ; 2.244      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.080     ; 2.242      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.079     ; 2.243      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
; 15.125 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.460       ; -0.077     ; 2.245      ;
+--------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                         ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                                         ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.004      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.795 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.003      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.005      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.796 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 2.003      ;
; 1.797 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.104      ; 2.005      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.102      ; 2.003      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.103      ; 2.004      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.006      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.006      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.006      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.006      ;
; 1.797 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.105      ; 2.006      ;
+-------+-------------------+-------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                   ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.201      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.201      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.201      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.200      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.200      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.200      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.103      ; 2.198      ;
; 1.991 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|stretch                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.190      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.197      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.190      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out8_reg[28]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.191      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.197      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[23]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[22]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.197      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[2]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[3]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[1]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[0]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[5]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[7]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[6]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_data_reg[4]                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|ack_error              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.197      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.190      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.190      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 2.192      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.104      ; 2.200      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.108      ; 2.204      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.107      ; 2.203      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.100      ; 2.196      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.102      ; 2.198      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rd[4]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rd[4]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.194      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.101      ; 2.197      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.992 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|count[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.105      ; 2.201      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.203      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.203      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.203      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.203      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 2.196      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.206      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.097      ; 2.194      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.206      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.106      ; 2.203      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.097      ; 2.194      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.206      ;
; 1.993 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_busy_reg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.109      ; 2.206      ;
+-------+---------------------------------------+---------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 2.752      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.095      ; 2.761      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.095      ; 2.761      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.095      ; 2.761      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.095      ; 2.761      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 2.752      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.757      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 2.752      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.101      ; 2.767      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 2.759      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.094      ; 2.760      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 2.759      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 2.759      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.094      ; 2.760      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 2.759      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.094      ; 2.760      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 2.759      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.094      ; 2.760      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 2.755      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.095      ; 2.761      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.098      ; 2.764      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.562 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.097      ; 2.763      ;
; 2.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 2.811      ;
; 2.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 2.811      ;
; 2.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 2.811      ;
; 2.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.082      ; 2.811      ;
; 2.734 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 2.929      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.608 ; 5.763        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[5]                   ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                              ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.476 ; 8.706        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.478 ; 8.708        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_address_reg0 ;
; 8.479 ; 8.709        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_we_reg       ;
; 8.481 ; 8.711        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a1~porta_datain_reg0  ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[15]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[20]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[30]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.515 ; 8.731        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scanlines_reg                                                                                                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[3]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[42]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[4]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[50]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[59]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                 ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                  ;
; 8.517 ; 8.733        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|buffer_select_reg                                                                                                    ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[0]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[1]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[2]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|colour_reg[3]                                                                                                        ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                  ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                                ;
; 8.518 ; 8.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:gen_scandouble_on:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.165 ; 10.395       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 10.166 ; 10.396       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 10.167 ; 10.397       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 10.201 ; 10.431       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[0]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[1]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dataOut[2]                                                                                                 ;
; 10.202 ; 10.432       ; 0.230          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.001                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.010                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.011                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.100                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|CurrState_sofCntl.101                                                         ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortReq                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|HCTxPortWEn                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[14]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFNearTime[15]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState[1]                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.10000                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXStreamStatus[1]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000001                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001001                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001100                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010110                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011010                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.011100                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|clearTXReq                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[1]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[2]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[3]                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|getPacketREn                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketArbiterReq                                                        ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|sendPacketPID[3]                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[0]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[1]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortData[2]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0010                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0101                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0110                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.0111                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1000                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1001                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1010                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1100                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|CurrState_sendPktCP.1101                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketWEn                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001011                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011                                  ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                             ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                            ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_td71:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                             ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari5200core_simplesdram:atari5200_simple_sdram1|atari5200core:atari5200_simple_sdram1|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                        ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                 ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0                    ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                 ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~portb_address_reg0                   ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[0]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[12]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[13]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[14]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[15]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[16]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[17]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[18]                                                                                                                                                                                                                                   ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[1]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[2]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[3]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[4]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[5]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[6]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[7]                                                                                                                                                                                                                                    ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[14]                                                                                                                                                                                                                                     ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_DI[6]                                                                                                                                                                                                                                      ;
; 17.227 ; 17.443       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_WIDTH_8BIT_ACCESS                                                                                                                                                                                                                          ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[10]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[11]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[19]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[20]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[21]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[22]                                                                                                                                                                                                                                   ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[8]                                                                                                                                                                                                                                    ;
; 17.228 ; 17.444       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[9]                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.451 ; 17.451       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.468 ; 17.468       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 89.518  ; 99.618       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 90.275  ; 100.375      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout   ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]         ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]         ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]         ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                     ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                           ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                   ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                   ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                   ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                          ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                          ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                           ;
; 99.445  ; 99.445       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                    ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.452  ; 99.452       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                   ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                          ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                            ;
; 99.459  ; 99.459       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                        ;
; 99.464  ; 99.464       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                          ;
; 99.618  ; 99.618       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                      ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                             ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                              ;
; 100.333 ; 100.549      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                             ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.483 ; 2.041 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.798 ; 6.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.635 ; 3.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 5.798 ; 6.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.690 ; 4.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 5.644 ; 5.950 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 1.747 ; 2.280 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; 2.754 ; 3.319 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.455 ; 6.849 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.802 ; 4.120 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 6.455 ; 6.849 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 3.797 ; 4.130 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.520 ; 5.831 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 2.246 ; 2.717 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; 2.759 ; 3.348 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.076 ; 3.880 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.123 ; 3.889 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 2.175 ; 2.624 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.256 ; -1.783 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.216 ; -2.601 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.804 ; -3.188 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.442 ; -2.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.672 ; -2.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.256 ; -1.783 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; -2.080 ; -2.644 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.722 ; -2.186 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.640 ; -3.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.405 ; -2.802 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.605 ; -2.972 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.604 ; -2.974 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.722 ; -2.186 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; -2.085 ; -2.673 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.528 ; -3.315 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.572 ; -3.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.671 ; -2.124 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.774 ; 1.628 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.764 ; 1.618 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.180 ; 2.124 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.874 ; 1.832 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.180 ; 2.124 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.623 ; 4.194 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 2.067 ; 2.200 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.607 ; 1.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.655 ; 4.199 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.055 ; 1.917 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.371 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.318 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.316 ; 1.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.932 ; 3.400 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.131 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.917 ; 3.385 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.885 ; 3.318 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.118 ; 1.084 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.108 ; 1.074 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.873 ; 3.306 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.086 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.096 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.099 ; 1.065 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.089 ; 1.055 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.097 ; 1.063 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.447 ; 1.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.447 ; 1.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.741 ; 1.690 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.204 ; 3.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.644 ; 1.773 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.194 ; 1.251 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.230 ; 3.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.624 ; 1.492 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.016 ; 1.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.355 ; 2.328 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.355 ; 2.328 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.355 ; 2.328 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.409 ; 2.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.594 ; 2.567 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.759 ; 2.732 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.773 ; 2.746 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.775 ; 2.748 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.277 ; 2.250 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.104 ; 2.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.026 ; 1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.026 ; 1.999 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.016 ; 1.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.029 ; 2.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.019 ; 1.992 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.029 ; 2.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.942 ; 2.566 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.040 ; 4.664 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 5.040 ; 4.664 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.721 ; 0.721 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.047 ; 1.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.047 ; 1.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.047 ; 1.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.099 ; 1.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.276 ; 1.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.435 ; 1.435 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.448 ; 1.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.451 ; 1.451 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 0.972 ; 0.972 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 0.807 ; 0.807 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.731 ; 0.731 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.731 ; 0.731 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.721 ; 0.721 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.734 ; 0.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.724 ; 0.724 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.734 ; 0.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.422 ; 2.061 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.610 ; 4.249 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 4.610 ; 4.249 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.058     ; 2.058     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.444     ; 2.444     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.444     ; 2.444     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.444     ; 2.444     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.499     ; 2.499     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.697     ; 2.697     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.881     ; 2.881     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.887     ; 2.887     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.890     ; 2.890     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.347     ; 2.347     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.159     ; 2.159     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.068     ; 2.068     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.068     ; 2.068     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.058     ; 2.058     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.073     ; 2.073     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.063     ; 2.063     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.073     ; 2.073     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.660     ; 3.036     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.950     ; 5.326     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 4.950     ; 5.326     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.762     ; 0.879     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.132     ; 1.249     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.132     ; 1.249     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.132     ; 1.249     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.185     ; 1.302     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.375     ; 1.492     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.552     ; 1.669     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.558     ; 1.675     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.561     ; 1.678     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.040     ; 1.157     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 0.859     ; 0.976     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.772     ; 0.889     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.772     ; 0.889     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.762     ; 0.879     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.776     ; 0.893     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.766     ; 0.883     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.776     ; 0.893     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.151     ; 2.512     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.523     ; 4.884     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 4.523     ; 4.884     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                         ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                                           ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                                ; 0.823  ; 0.149 ; 4.503    ; 1.795   ; 5.517               ;
;  FPGA_CLK                                                                       ; 93.429 ; 0.193 ; N/A      ; N/A     ; 89.442              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.823  ; 0.187 ; 4.503    ; 2.562   ; 5.517               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.356  ; 0.149 ; 5.935    ; 1.991   ; 17.014              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 9.518  ; 0.187 ; 11.907   ; 1.795   ; 8.428               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 17.423              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 11.825 ; 0.182 ; N/A      ; N/A     ; 10.114              ;
; Design-wide TNS                                                                 ; 0.0    ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                       ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000  ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046  ; 3.153  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.012  ; 3.119  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040  ; 3.147  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038  ; 3.145  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034  ; 3.141  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046  ; 3.153  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032  ; 3.139  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.036  ; 3.143  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.026  ; 3.133  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024  ; 3.131  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014  ; 3.121  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024  ; 3.131  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 12.289 ; 12.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 7.496  ; 7.732  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 12.289 ; 12.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 7.681  ; 7.968  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 11.937 ; 12.214 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.595  ; 3.844  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; 5.864  ; 5.983  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 13.706 ; 14.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 7.933  ; 8.058  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 13.706 ; 14.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 7.917  ; 8.187  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 11.855 ; 12.204 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 4.549  ; 4.747  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; 5.967  ; 6.020  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.339  ; 6.668  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.465  ; 6.740  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.402  ; 4.561  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864  ; 0.997  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; 0.864  ; 0.997  ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.017 ; -1.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.256 ; -1.783 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.216 ; -2.601 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.804 ; -3.188 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.442 ; -2.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -2.672 ; -2.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.256 ; -1.783 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[5]    ; FPGA_CLK   ; -2.080 ; -2.644 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.722 ; -2.186 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.640 ; -3.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.405 ; -2.802 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.605 ; -2.972 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.604 ; -2.974 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.722 ; -2.186 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[5]    ; FPGA_CLK   ; -2.085 ; -2.673 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.528 ; -3.315 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.572 ; -3.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.671 ; -2.124 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313 ; 3.077 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317 ; 3.081 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326 ; 3.090 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336 ; 3.100 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346 ; 3.110 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323 ; 3.087 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325 ; 3.089 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578 ; 4.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590 ; 4.140 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.617 ; 3.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637 ; 4.189 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633 ; 4.185 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563 ; 2.365 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507 ; 3.264 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519 ; 3.276 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639 ; 3.382 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.633 ; 3.376 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.623 ; 3.366 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648 ; 4.200 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614 ; 3.357 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624 ; 3.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.327 ; 4.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.812 ; 4.241 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 4.327 ; 4.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335 ; 3.099 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345 ; 3.109 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.083 ; 7.175 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.589 ; 4.326 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.784 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.998 ; 7.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 4.118 ; 4.363 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.378 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 9.107 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.808 ; 2.778 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.382 ; 5.730 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.578 ; 2.528 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.360 ; 5.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.266 ; 5.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.516 ; 2.399 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.506 ; 2.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.255 ; 5.548 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.484 ; 2.367 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.494 ; 2.377 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.496 ; 2.379 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.486 ; 2.369 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.495 ; 2.378 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.355 ; 1.211 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.345 ; 1.201 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.447 ; 1.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.447 ; 1.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.741 ; 1.690 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.204 ; 3.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.644 ; 1.773 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.194 ; 1.251 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.230 ; 3.771 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.624 ; 1.492 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.998 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.944 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.920 ; 0.939 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.537 ; 3.005 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.736 ; 0.798 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.522 ; 2.990 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.488 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.721 ; 0.687 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.711 ; 0.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.477 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.690 ; 0.656 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.702 ; 0.668 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.700 ; 0.666 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_P         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; USB2_P       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; USB2_N       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                               ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1          ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6871       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4588624    ; 0        ; 1831     ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 74         ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1289       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                       ; false path ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                       ; FPGA_CLK                                                                       ; 352        ; 1        ; 1        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; false path ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10097      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1          ; 248      ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6871       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4588624    ; 0        ; 1831     ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; false path ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 74         ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1289       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                       ; false path ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                       ; FPGA_CLK                                                                       ; 352        ; 1        ; 1        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; false path ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; 10097      ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                            ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 694        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1674       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 177        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; false path ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                             ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths   ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 694        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1674       ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] ; 177        ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                            ; false path ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 33    ; 33   ;
; Unconstrained Input Port Paths  ; 103   ; 103  ;
; Unconstrained Output Ports      ; 57    ; 57   ;
; Unconstrained Output Port Paths ; 76    ; 76   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Warning (125092): Tcl Script File pal_pll.qip not found
    Info (125063): set_global_assignment -name QIP_FILE pal_pll.qip
Warning (125092): Tcl Script File pll_downstream_pal.qip not found
    Info (125063): set_global_assignment -name QIP_FILE pll_downstream_pal.qip
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Wed Sep 11 22:12:33 2019
Info: Command: quartus_sta atari5200core -c atari5200core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari5200core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 11 -multiply_by 63 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 236.25 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 0.823
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.823         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.356         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.518         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    11.825         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    93.429         0.000 FPGA_CLK 
Info (332146): Worst-case hold slack is 0.409
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.409         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.454         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.504         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 4.503
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     4.503         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.935         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    11.907         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 3.970
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.970         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     4.257         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     5.497         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 5.517
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.517         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.428         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.115         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.014         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.423         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.442         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 1.061
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.061         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.848         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.907         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.458         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    93.521         0.000 FPGA_CLK 
Info (332146): Worst-case hold slack is 0.385
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.385         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.402         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.403         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.470         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 5.070
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.070         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     6.462         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    12.318         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 3.566
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.566         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     3.864         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.979         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 5.517
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.517         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.431         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.114         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.031         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.426         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.446         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 3.525
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.525         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.447         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    13.955         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    16.941         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    96.738         0.000 FPGA_CLK 
Info (332146): Worst-case hold slack is 0.149
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.149         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.182         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.193         0.000 FPGA_CLK 
Info (332146): Worst-case recovery slack is 8.154
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     8.154         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.994         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    14.867         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is 1.795
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.795         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     1.991         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.562         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case minimum pulse width slack is 5.605
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.605         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     8.476         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    10.165         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.206         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.437         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.518         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 535 megabytes
    Info: Processing ended: Wed Sep 11 22:12:45 2019
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:14


