TimeQuest Timing Analyzer report for atari800core
Sat Jul 13 22:17:07 2019
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 15. Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 16. Slow 1200mV 85C Model Setup: 'FPGA_CLK'
 17. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 18. Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 19. Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Hold: 'FPGA_CLK'
 21. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 22. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 23. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 24. Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 25. Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 26. Slow 1200mV 85C Model Recovery: 'FPGA_CLK'
 27. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 28. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 29. Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 30. Slow 1200mV 85C Model Removal: 'FPGA_CLK'
 31. Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 32. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 33. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 34. Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 35. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 36. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 37. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 38. Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 39. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 40. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 42. Setup Times
 43. Hold Times
 44. Clock to Output Times
 45. Minimum Clock to Output Times
 46. Output Enable Times
 47. Minimum Output Enable Times
 48. Output Disable Times
 49. Minimum Output Disable Times
 50. Slow 1200mV 85C Model Metastability Report
 51. Slow 1200mV 0C Model Fmax Summary
 52. Slow 1200mV 0C Model Setup Summary
 53. Slow 1200mV 0C Model Hold Summary
 54. Slow 1200mV 0C Model Recovery Summary
 55. Slow 1200mV 0C Model Removal Summary
 56. Slow 1200mV 0C Model Minimum Pulse Width Summary
 57. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 58. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 59. Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 60. Slow 1200mV 0C Model Setup: 'FPGA_CLK'
 61. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 62. Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 63. Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 64. Slow 1200mV 0C Model Hold: 'FPGA_CLK'
 65. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 66. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 68. Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 69. Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 70. Slow 1200mV 0C Model Recovery: 'FPGA_CLK'
 71. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 72. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 73. Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 74. Slow 1200mV 0C Model Removal: 'FPGA_CLK'
 75. Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 76. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 77. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 78. Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 79. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
 80. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
 81. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
 82. Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
 83. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
 84. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
 85. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 86. Setup Times
 87. Hold Times
 88. Clock to Output Times
 89. Minimum Clock to Output Times
 90. Output Enable Times
 91. Minimum Output Enable Times
 92. Output Disable Times
 93. Minimum Output Disable Times
 94. Slow 1200mV 0C Model Metastability Report
 95. Fast 1200mV 0C Model Setup Summary
 96. Fast 1200mV 0C Model Hold Summary
 97. Fast 1200mV 0C Model Recovery Summary
 98. Fast 1200mV 0C Model Removal Summary
 99. Fast 1200mV 0C Model Minimum Pulse Width Summary
100. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
101. Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
102. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
103. Fast 1200mV 0C Model Setup: 'FPGA_CLK'
104. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
105. Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
106. Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
107. Fast 1200mV 0C Model Hold: 'FPGA_CLK'
108. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
109. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
110. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
111. Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
112. Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
113. Fast 1200mV 0C Model Recovery: 'FPGA_CLK'
114. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
115. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
116. Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
117. Fast 1200mV 0C Model Removal: 'FPGA_CLK'
118. Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
119. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
120. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
121. Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
122. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'
123. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'
124. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'
125. Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'
126. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'
127. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'
128. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
129. Setup Times
130. Hold Times
131. Clock to Output Times
132. Minimum Clock to Output Times
133. Output Enable Times
134. Minimum Output Enable Times
135. Output Disable Times
136. Minimum Output Disable Times
137. Fast 1200mV 0C Model Metastability Report
138. Multicorner Timing Analysis Summary
139. Setup Times
140. Hold Times
141. Clock to Output Times
142. Minimum Clock to Output Times
143. Board Trace Model Assignments
144. Input Transition Times
145. Slow Corner Signal Integrity Metrics
146. Fast Corner Signal Integrity Metrics
147. Setup Transfers
148. Hold Transfers
149. Recovery Transfers
150. Removal Transfers
151. Report TCCS
152. Report RSKM
153. Unconstrained Paths
154. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.33        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ;  11.1%      ;
;     Processors 5-6         ; < 0.1%      ;
;     Processors 7-12        ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sat Jul 13 22:16:59 2019 ;
+------------------+--------+--------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; Clock Name                                                                          ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                             ; Source                                                                                ; Targets                                                                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.747  ; 85.13 MHz ; 0.000 ; 5.873   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.747  ; 85.13 MHz ; 7.341 ; 13.214  ; 50.00      ; 1         ; 3           ; 225.0 ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Generated ; 17.621  ; 56.75 MHz ; 0.000 ; 8.810   ; 50.00      ; 1         ; 2           ;       ;        ;           ;            ; false    ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] } ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 35.242  ; 28.38 MHz ; 0.000 ; 17.621  ; 50.00      ; 40        ; 227         ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                            ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                                    ;                                                                                       ; { FPGA_CLK }                                                                            ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; Generated ; 20.833  ; 48.0 MHz  ; 0.000 ; 10.416  ; 50.00      ; 5         ; 48          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                           ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                 ; { usb_pll|altpll_component|auto_generated|pll1|clk[0] }                                 ;
+-------------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                                                                  ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 34.99 MHz  ; 34.99 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 72.42 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
; 91.59 MHz  ; 91.59 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 104.98 MHz ; 104.98 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 134.43 MHz ; 134.43 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                          ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.101 ; -158.000      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.117 ; -2.117        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.199 ; -39.377       ;
; FPGA_CLK                                                                            ; -0.229 ; -0.229        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.506  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.880  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.121 ; -41.362       ;
; FPGA_CLK                                                                            ; -0.721 ; -0.721        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.435  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.455  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.455  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.965 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                       ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.487 ; -22.359       ;
; FPGA_CLK                                                                            ; -0.458 ; -11.870       ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.304  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.411  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.484 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.486 ; -12.373       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.264  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.343  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.870  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.386  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.570  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.696  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.507  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.346  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.187 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.589 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.483 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -4.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.631     ; 1.442      ;
; -4.062 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.631     ; 1.403      ;
; -3.861 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.177     ; 1.656      ;
; -3.766 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.094      ;
; -3.750 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 1.093      ;
; -3.748 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.076      ;
; -3.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.073      ;
; -3.744 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.644     ; 1.072      ;
; -3.677 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.201     ; 1.448      ;
; -3.663 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.201     ; 1.434      ;
; -3.613 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.201     ; 1.384      ;
; -3.590 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 0.933      ;
; -3.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 0.910      ;
; -3.566 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 0.909      ;
; -3.565 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 0.908      ;
; -3.553 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.643     ; 0.882      ;
; -3.541 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.629     ; 0.884      ;
; -3.330 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 1.094      ;
; -3.330 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 1.094      ;
; -3.329 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 1.129      ;
; -3.302 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 1.071      ;
; -3.297 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 1.066      ;
; -3.277 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 1.046      ;
; -3.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 0.933      ;
; -3.169 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 0.933      ;
; -3.168 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 0.932      ;
; -3.145 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 0.909      ;
; -3.144 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.208     ; 0.908      ;
; -3.140 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.202     ; 0.910      ;
; -3.139 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 0.908      ;
; -3.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.202     ; 0.908      ;
; -3.138 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 0.907      ;
; -3.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.202     ; 0.907      ;
; -3.137 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.202     ; 0.907      ;
; -3.120 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.210     ; 0.882      ;
; -3.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.202     ; 0.883      ;
; -3.113 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 0.882      ;
; -3.112 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.203     ; 0.881      ;
; -3.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.909      ;
; -3.109 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.909      ;
; -3.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.908      ;
; -3.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.908      ;
; -3.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.908      ;
; -3.108 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.908      ;
; -3.106 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.172     ; 0.906      ;
; -3.093 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.182     ; 0.883      ;
; -3.092 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.182     ; 0.882      ;
; 1.683  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 9.815      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 1.890  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.609      ;
; 2.144  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 9.367      ;
; 2.144  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 9.367      ;
; 2.162  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 9.348      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.168  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.344      ;
; 2.190  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 9.318      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.408  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.091      ;
; 2.425  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.074      ;
; 2.425  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.074      ;
; 2.425  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 9.074      ;
; 2.462  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.050      ;
; 2.462  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.050      ;
; 2.462  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.050      ;
; 2.462  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 9.050      ;
; 2.481  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 9.017      ;
; 2.481  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 9.017      ;
; 2.481  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.161     ; 9.017      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.519  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 8.993      ;
; 2.577  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.904      ;
; 2.594  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 8.884      ;
; 2.596  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.181     ; 8.882      ;
; 2.626  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.854      ;
; 2.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.820      ;
; 2.664  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.820      ;
; 2.694  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.178     ; 8.787      ;
; 2.701  ; ram_do_reg[7]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[32]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.179     ; 8.779      ;
; 2.715  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 8.769      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                            ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -2.117 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.955     ; 1.397      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.199 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.429      ;
; -1.160 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.390      ;
; -1.159 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.389      ;
; -1.147 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.377      ;
; -1.135 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.364      ;
; -1.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.332      ;
; -1.085 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.315      ;
; -1.065 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.295      ;
; -1.041 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.270      ;
; -1.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.236      ;
; -0.986 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.216      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.180      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.190      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.176      ;
; -0.956 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.333      ; 2.189      ;
; -0.953 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.169      ;
; -0.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.171      ;
; -0.940 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.169      ;
; -0.937 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.153      ;
; -0.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.165      ;
; -0.931 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.161      ;
; -0.928 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.157      ;
; -0.920 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.150      ;
; -0.916 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.145      ;
; -0.916 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.146      ;
; -0.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.142      ;
; -0.912 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.141      ;
; -0.902 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.132      ;
; -0.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.117      ;
; -0.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.126      ;
; -0.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.125      ;
; -0.893 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.123      ;
; -0.889 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.105      ;
; -0.881 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.097      ;
; -0.880 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 2.097      ;
; -0.869 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.099      ;
; -0.868 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.098      ;
; -0.860 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.317      ; 2.077      ;
; -0.855 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.329      ; 2.084      ;
; -0.853 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.330      ; 2.083      ;
; -0.852 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.316      ; 2.068      ;
; 4.961  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.829     ; 7.018      ;
; 5.092  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.829     ; 6.887      ;
; 6.678  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.036      ; 7.776      ;
; 6.849  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 5.522      ;
; 6.880  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.034      ; 7.572      ;
; 7.055  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.034      ; 7.397      ;
; 7.090  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 5.275      ;
; 7.091  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 5.274      ;
; 7.103  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.034      ; 7.349      ;
; 7.183  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 5.188      ;
; 7.195  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.036      ; 7.259      ;
; 7.205  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.036      ; 7.249      ;
; 7.246  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 5.119      ;
; 7.257  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 4.034      ; 7.195      ;
; 7.317  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 5.048      ;
; 7.394  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.971      ;
; 7.466  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.899      ;
; 7.592  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.774      ;
; 7.596  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 4.775      ;
; 7.622  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.743      ;
; 7.624  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.741      ;
; 7.627  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.739      ;
; 7.640  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.726      ;
; 7.782  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 4.589      ;
; 7.838  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.528      ;
; 7.882  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.484      ;
; 7.930  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 4.441      ;
; 7.958  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.407      ;
; 7.972  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.442     ; 4.394      ;
; 8.001  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.437     ; 4.370      ;
; 8.028  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.443     ; 4.337      ;
; 8.055  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.441     ; 4.312      ;
; 8.371  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.441     ; 3.996      ;
; 8.667  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.441     ; 3.700      ;
; 9.050  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.114     ; 1.253      ;
; 9.210  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.114     ; 1.093      ;
; 9.915  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.081     ; 10.838     ;
; 9.915  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.081     ; 10.838     ;
; 9.990  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.081     ; 10.763     ;
; 10.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.704     ;
; 10.036 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.704     ;
; 10.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.679     ;
; 10.061 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.679     ;
; 10.111 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.629     ;
; 10.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.618     ;
; 10.122 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.618     ;
; 10.136 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.604     ;
; 10.197 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.543     ;
; 10.300 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.440     ;
; 10.300 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.440     ;
; 10.326 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.414     ;
; 10.326 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.414     ;
; 10.375 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.365     ;
; 10.401 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.339     ;
; 10.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.332     ;
; 10.408 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.332     ;
; 10.483 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.257     ;
; 10.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.044     ;
; 10.696 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.094     ; 10.044     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                              ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.229  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.645      ;
; 93.096  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.872     ; 6.033      ;
; 95.790  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.660      ; 2.069      ;
; 196.361 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.560      ;
; 196.391 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.530      ;
; 196.483 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.438      ;
; 196.506 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.415      ;
; 196.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.414      ;
; 196.536 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.385      ;
; 196.537 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.384      ;
; 196.596 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.325      ;
; 196.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.296      ;
; 196.629 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.292      ;
; 196.652 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.269      ;
; 196.653 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.268      ;
; 196.653 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.268      ;
; 196.682 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.239      ;
; 196.683 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.238      ;
; 196.683 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.238      ;
; 196.742 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.179      ;
; 196.749 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.172      ;
; 196.754 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.167      ;
; 196.771 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.150      ;
; 196.775 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.146      ;
; 196.796 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.125      ;
; 196.798 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.123      ;
; 196.799 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.122      ;
; 196.799 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.122      ;
; 196.826 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.095      ;
; 196.828 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.093      ;
; 196.829 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.092      ;
; 196.829 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.092      ;
; 196.883 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.038      ;
; 196.888 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.033      ;
; 196.895 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.026      ;
; 196.900 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.021      ;
; 196.917 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.004      ;
; 196.921 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 3.000      ;
; 196.922 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.999      ;
; 196.942 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.979      ;
; 196.944 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.977      ;
; 196.945 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.976      ;
; 196.945 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.976      ;
; 196.947 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.974      ;
; 196.972 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.949      ;
; 196.974 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.947      ;
; 196.975 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.946      ;
; 196.975 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.946      ;
; 196.977 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.944      ;
; 197.029 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.892      ;
; 197.034 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.887      ;
; 197.035 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.886      ;
; 197.041 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.880      ;
; 197.046 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.875      ;
; 197.063 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.858      ;
; 197.067 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.854      ;
; 197.068 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.853      ;
; 197.068 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.853      ;
; 197.088 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.833      ;
; 197.089 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.832      ;
; 197.090 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.831      ;
; 197.091 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.830      ;
; 197.091 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.830      ;
; 197.093 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.828      ;
; 197.118 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.803      ;
; 197.119 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.802      ;
; 197.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.801      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.800      ;
; 197.121 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.800      ;
; 197.123 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.798      ;
; 197.175 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.746      ;
; 197.180 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.741      ;
; 197.181 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.740      ;
; 197.181 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.740      ;
; 197.187 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.734      ;
; 197.192 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.729      ;
; 197.209 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.712      ;
; 197.213 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.708      ;
; 197.214 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.707      ;
; 197.214 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.707      ;
; 197.214 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.707      ;
; 197.234 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.687      ;
; 197.235 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.686      ;
; 197.236 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.685      ;
; 197.237 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.684      ;
; 197.238 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.079     ; 2.684      ;
; 197.239 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.682      ;
; 197.240 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.681      ;
; 197.264 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.657      ;
; 197.265 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.656      ;
; 197.266 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.655      ;
; 197.267 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.654      ;
; 197.267 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.654      ;
; 197.269 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.652      ;
; 197.270 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.651      ;
; 197.321 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.600      ;
; 197.325 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.596      ;
; 197.326 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.595      ;
; 197.327 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.594      ;
; 197.327 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.080     ; 2.594      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                           ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.506 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 4.981      ;
; 0.580 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 4.915      ;
; 0.626 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 4.861      ;
; 0.704 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.795      ;
; 0.824 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.675      ;
; 0.842 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.644      ;
; 0.842 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.644      ;
; 0.897 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.589      ;
; 0.974 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.512      ;
; 0.974 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.512      ;
; 1.029 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 4.457      ;
; 1.038 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.450      ;
; 1.170 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.166     ; 4.318      ;
; 1.209 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 4.278      ;
; 1.293 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.150     ; 4.211      ;
; 1.297 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 4.204      ;
; 1.341 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.167     ; 4.146      ;
; 1.353 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.146      ;
; 1.353 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.146      ;
; 1.353 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.146      ;
; 1.353 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.146      ;
; 1.429 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 4.072      ;
; 1.485 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.014      ;
; 1.485 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.014      ;
; 1.485 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.014      ;
; 1.485 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 4.014      ;
; 1.626 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 3.873      ;
; 1.666 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.830      ;
; 1.758 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.155     ; 3.741      ;
; 1.788 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.695      ;
; 1.814 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.145     ; 3.695      ;
; 1.833 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.660      ;
; 1.952 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.544      ;
; 1.956 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.148     ; 3.550      ;
; 1.960 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.524      ;
; 1.997 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.172     ; 3.485      ;
; 2.023 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.161     ; 3.470      ;
; 2.024 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.598      ;
; 2.025 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.597      ;
; 2.025 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.597      ;
; 2.026 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.596      ;
; 2.028 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.594      ;
; 2.029 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.593      ;
; 2.029 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.593      ;
; 2.031 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 3.591      ;
; 2.047 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.454      ;
; 2.101 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.145     ; 3.408      ;
; 2.179 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.153     ; 3.322      ;
; 2.183 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.157     ; 3.314      ;
; 2.255 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.156     ; 3.243      ;
; 2.272 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.341      ;
; 2.273 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.340      ;
; 2.273 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.340      ;
; 2.274 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.339      ;
; 2.276 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.337      ;
; 2.277 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.336      ;
; 2.277 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.336      ;
; 2.279 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.334      ;
; 2.286 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.335      ;
; 2.289 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.955     ; 1.397      ;
; 2.341 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.160     ; 3.153      ;
; 2.361 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.264      ;
; 2.385 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.118      ;
; 2.410 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.163     ; 3.211      ;
; 2.448 ; SDRAM_ADDR[2]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 3.055      ;
; 2.457 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.168      ;
; 2.458 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.159     ; 3.167      ;
; 2.470 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.156      ;
; 2.496 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 3.130      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.512 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.101      ;
; 2.522 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.091      ;
; 2.522 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.091      ;
; 2.522 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.091      ;
; 2.522 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 3.091      ;
; 2.547 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 3.067      ;
; 2.614 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 2.889      ;
; 2.624 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.170     ; 2.990      ;
; 2.671 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.945      ;
; 2.704 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.912      ;
; 2.705 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.911      ;
; 2.706 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.910      ;
; 2.737 ; SDRAM_ADDR[10]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.162     ; 2.755      ;
; 2.765 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 2.738      ;
; 2.767 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.151     ; 2.736      ;
; 2.778 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 2.848      ;
; 2.782 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 2.844      ;
; 2.791 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.825      ;
; 2.840 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.776      ;
; 2.840 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.168     ; 2.776      ;
; 2.926 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 2.687      ;
; 2.926 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.171     ; 2.687      ;
; 2.956 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 2.670      ;
; 2.957 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 2.669      ;
; 2.957 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.158     ; 2.669      ;
; 2.977 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.169     ; 2.638      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                         ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 4.880  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.955     ; 1.743      ;
; 7.432  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.250     ; 9.720      ;
; 7.721  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.205     ; 9.476      ;
; 7.950  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 9.248      ;
; 7.982  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 9.216      ;
; 7.997  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 9.201      ;
; 8.051  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 9.147      ;
; 8.056  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.243     ; 9.103      ;
; 8.073  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.205     ; 9.124      ;
; 8.095  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 9.142      ;
; 8.098  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 9.100      ;
; 8.348  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.251     ; 8.803      ;
; 8.461  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.204     ; 8.737      ;
; 8.482  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 8.755      ;
; 8.502  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 8.735      ;
; 8.835  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 8.402      ;
; 8.881  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[2]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.208     ; 8.313      ;
; 8.888  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 8.394      ;
; 8.890  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 8.346      ;
; 8.957  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.210     ; 8.235      ;
; 8.987  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 8.295      ;
; 8.989  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 8.294      ;
; 9.000  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 8.237      ;
; 9.078  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 8.205      ;
; 9.082  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 8.154      ;
; 9.083  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 8.199      ;
; 9.139  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 8.097      ;
; 9.181  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 8.102      ;
; 9.221  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 8.061      ;
; 9.251  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 8.032      ;
; 9.267  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 8.016      ;
; 9.272  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.210     ; 7.920      ;
; 9.310  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 7.926      ;
; 9.326  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 7.918      ;
; 9.336  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.947      ;
; 9.405  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.878      ;
; 9.410  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.873      ;
; 9.477  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.806      ;
; 9.488  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 7.756      ;
; 9.520  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.763      ;
; 9.568  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.243     ; 7.591      ;
; 9.582  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.700      ;
; 9.595  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.687      ;
; 9.618  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.665      ;
; 9.647  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.636      ;
; 9.648  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.634      ;
; 9.661  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.622      ;
; 9.671  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 7.565      ;
; 9.677  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.166     ; 7.559      ;
; 9.678  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.605      ;
; 9.718  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 7.526      ;
; 9.751  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.532      ;
; 9.755  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 7.489      ;
; 9.803  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.480      ;
; 9.812  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 7.432      ;
; 9.830  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.453      ;
; 9.852  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.430      ;
; 9.906  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.377      ;
; 9.930  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.352      ;
; 9.944  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.339      ;
; 9.944  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 7.338      ;
; 9.962  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.321      ;
; 9.969  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.314      ;
; 10.038 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.245      ;
; 10.113 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.170      ;
; 10.118 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.165      ;
; 10.230 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.053      ;
; 10.254 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 7.029      ;
; 10.302 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.981      ;
; 10.312 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.971      ;
; 10.332 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 6.950      ;
; 10.354 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.929      ;
; 10.375 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.458     ; 6.699      ;
; 10.389 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.894      ;
; 10.399 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.884      ;
; 10.446 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.165     ; 6.791      ;
; 10.518 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.765      ;
; 10.582 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.662      ;
; 10.596 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.648      ;
; 10.641 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.603      ;
; 10.643 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.461     ; 6.428      ;
; 10.686 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.558      ;
; 10.747 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 6.453      ;
; 10.825 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.467     ; 6.240      ;
; 10.878 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.458     ; 6.196      ;
; 10.914 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.369      ;
; 10.983 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.467     ; 6.082      ;
; 10.986 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.258      ;
; 11.020 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.461     ; 6.051      ;
; 11.031 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.213      ;
; 11.054 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.190      ;
; 11.083 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.120     ; 6.199      ;
; 11.145 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 6.099      ;
; 11.154 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.129      ;
; 11.205 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.458     ; 5.869      ;
; 11.230 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.119     ; 6.053      ;
; 11.328 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.201     ; 5.873      ;
; 11.366 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.158     ; 5.878      ;
; 11.375 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.705      ;
; 11.376 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.452     ; 5.704      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.121 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.642      ; 1.841      ;
; -1.110 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.642      ; 1.852      ;
; -1.103 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.846      ;
; -1.102 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.861      ;
; -1.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.848      ;
; -1.095 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.854      ;
; -1.094 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.869      ;
; -1.089 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.874      ;
; -1.086 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.877      ;
; -1.086 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.863      ;
; -1.081 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.642      ; 1.881      ;
; -1.080 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.869      ;
; -1.079 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.884      ;
; -1.078 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.885      ;
; -1.070 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.879      ;
; -1.066 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.897      ;
; -1.055 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.908      ;
; -1.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.919      ;
; -1.044 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.919      ;
; -1.039 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.642      ; 1.923      ;
; -1.038 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.925      ;
; -1.035 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.928      ;
; -1.031 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.918      ;
; -1.027 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.936      ;
; -1.022 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.941      ;
; -1.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.944      ;
; -1.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.930      ;
; -1.004 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 1.945      ;
; -0.998 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 1.965      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.645      ; 2.005      ;
; -0.931 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 2.018      ;
; -0.901 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.062      ;
; -0.897 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.066      ;
; -0.894 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.629      ; 2.055      ;
; -0.879 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.084      ;
; -0.878 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.085      ;
; -0.855 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.108      ;
; -0.849 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.114      ;
; -0.844 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.119      ;
; -0.832 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.131      ;
; -0.826 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.643      ; 2.137      ;
; 0.454  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                            ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[0]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferInIndex[1]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutIndex[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|RxWireActive          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[4]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXFifoWEn                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|CRCResult[0]                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|SIERxTimeOutEn                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01101                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|delCnt[0]                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00110                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00111                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                  ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.721 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.549      ; 4.206      ;
; 0.501  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 0.793      ;
; 0.509  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 0.801      ;
; 0.698  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 0.990      ;
; 0.746  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.038      ;
; 0.746  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.038      ;
; 0.747  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.039      ;
; 0.748  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.749  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.040      ;
; 0.751  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.042      ;
; 0.762  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.054      ;
; 0.763  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.055      ;
; 0.764  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.056      ;
; 0.764  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.056      ;
; 0.764  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.056      ;
; 0.765  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.057      ;
; 0.766  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.057      ;
; 0.766  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.058      ;
; 0.767  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.059      ;
; 0.773  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.064      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.008  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.300      ;
; 1.100  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.392      ;
; 1.100  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.392      ;
; 1.101  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.392      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.102  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.393      ;
; 1.103  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.394      ;
; 1.108  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.401      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.109  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.400      ;
; 1.110  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.401      ;
; 1.112  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.403      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.409      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.409      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.410      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.410      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.409      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.411      ;
; 1.119  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.410      ;
; 1.121  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.412      ;
; 1.125  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.417      ;
; 1.125  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.417      ;
; 1.127  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.418      ;
; 1.127  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.419      ;
; 1.128  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.420      ;
; 1.134  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.426      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.427      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.428      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.429      ;
; 1.231  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.523      ;
; 1.231  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.523      ;
; 1.232  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.523      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.233  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.524      ;
; 1.234  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.525      ;
; 1.240  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.532      ;
; 1.240  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.532      ;
; 1.241  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.532      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.242  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.533      ;
; 1.243  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.534      ;
; 1.248  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.540      ;
; 1.248  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.540      ;
; 1.248  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.540      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.541      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.080      ; 1.541      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
; 1.249  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.079      ; 1.540      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                 ; To Node                                                                                                                                                                                                                        ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.435 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.435 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.099      ; 0.746      ;
; 0.446 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.471      ; 1.171      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[16]                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                              ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|a_r[7]                                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; paddle_mode_reg                                                                                                                                                                                           ; paddle_mode_reg                                                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[1]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcycle_state_reg[0]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                            ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[6]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[3]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[0]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|full_dff                         ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|full_dff                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[6]                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[0]                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[1]                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[0]                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|state_reg[1]                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|data_in_reg                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|latch_delay_line:stimer_delay|data_in_reg                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|latch_delay_line:wsync_delay|data_in_reg                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|latch_delay_line:wsync_delay|data_in_reg                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[1]                                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[1]                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_request_reg                                                                                      ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_request_complete_reg                                                                             ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.746      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.467 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.758      ;
; 0.520 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.811      ;
; 0.527 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.818      ;
; 0.530 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.821      ;
; 0.546 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.836      ;
; 0.547 ; seq_reg[10]                                                                                            ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.837      ;
; 0.645 ; ram_bena_reg[1]                                                                                        ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.935      ;
; 0.645 ; ram_bena_reg[0]                                                                                        ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.935      ;
; 0.684 ; seq_reg[9]                                                                                             ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.974      ;
; 0.702 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 0.992      ;
; 0.733 ; seq_reg[8]                                                                                             ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.023      ;
; 0.738 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.029      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.030      ;
; 0.740 ; seq_reg[2]                                                                                             ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.031      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.742 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                              ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.033      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.050      ;
; 0.759 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.050      ;
; 0.790 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.080      ;
; 0.805 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.095      ;
; 0.826 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.116      ;
; 0.936 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.227      ;
; 0.946 ; seq_reg[3]                                                                                             ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.237      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.303      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.315      ;
; 1.064 ; sdram_request_reg                                                                                      ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.354      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.384      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.384      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.094 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.385      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.391      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.392      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.393      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.394      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.400      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.401      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.402      ;
; 1.112 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.403      ;
; 1.112 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.403      ;
; 1.135 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.425      ;
; 1.143 ; seq_reg[4]                                                                                             ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.434      ;
; 1.171 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.460      ;
; 1.197 ; seq_reg[1]                                                                                             ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.488      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.515      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.516      ;
; 1.227 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.518      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.524      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.234 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.525      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.532      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.533      ;
; 1.243 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.534      ;
; 1.243 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.534      ;
; 1.250 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.541      ;
; 1.251 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.542      ;
; 1.252 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.543      ;
; 1.252 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.543      ;
; 1.276 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.566      ;
; 1.278 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.567      ;
; 1.283 ; seq_reg[7]                                                                                             ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.573      ;
; 1.285 ; seq_reg[1]                                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.576      ;
; 1.288 ; seq_reg[9]                                                                                             ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.578      ;
; 1.299 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.590      ;
; 1.303 ; sdram_ctrl:sdram_controller|r_rddata[15]                                                               ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.257      ; 1.772      ;
; 1.309 ; seq_reg[11]                                                                                            ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.600      ;
; 1.319 ; seq_reg[0]                                                                                             ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.609      ;
; 1.330 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.026      ; 1.482      ;
; 1.330 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.026      ; 1.482      ;
; 1.330 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.026      ; 1.482      ;
; 1.343 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.634      ;
; 1.352 ; seq_reg[11]                                                                                            ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.643      ;
; 1.352 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.641      ;
; 1.352 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.641      ;
; 1.355 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.077      ; 1.644      ;
; 1.364 ; sdram_ctrl:sdram_controller|r_rddata[2]                                                                ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.262      ; 1.838      ;
; 1.364 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.655      ;
; 1.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.165      ; 1.850      ;
; 1.365 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.656      ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                     ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                        ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                              ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.455 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                            ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.746      ;
; 0.467 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.758      ;
; 0.501 ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                                             ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.792      ;
; 0.502 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.793      ;
; 0.502 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.794      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.503 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.793      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.795      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.504 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.794      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.796      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.505 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.795      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.797      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.506 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.796      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.507 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.797      ;
; 0.511 ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                    ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.802      ;
; 0.556 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.594      ; 1.514      ;
; 0.687 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.978      ;
; 0.688 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.979      ;
; 0.689 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.979      ;
; 0.698 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.988      ;
; 0.698 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.988      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.991      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.700 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.990      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 0.992      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.991      ;
; 0.701 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.078      ; 0.991      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.965 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.675     ; 1.190      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.487 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.341      ; 3.728      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.484 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.340      ; 3.724      ;
; -2.290 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.341      ; 3.596      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
; -2.287 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.340      ; 3.592      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.458 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.649      ; 4.874      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.456 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.650      ; 4.873      ;
; -0.444 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.633      ; 4.844      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                              ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.304 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.385     ; 3.827      ;
; 7.308 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.389     ; 3.819      ;
; 7.311 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.821      ;
; 7.311 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.821      ;
; 7.311 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.384     ; 3.821      ;
; 7.312 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.385     ; 3.819      ;
; 7.312 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.385     ; 3.819      ;
; 7.312 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.385     ; 3.819      ;
; 7.316 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.258     ; 3.954      ;
; 7.317 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.827      ;
; 7.320 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.262     ; 3.946      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.201     ; 4.004      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 4.002      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.003      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.948      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.948      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.257     ; 3.948      ;
; 7.323 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.003      ;
; 7.324 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 4.001      ;
; 7.324 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 4.001      ;
; 7.324 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.258     ; 3.946      ;
; 7.324 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.258     ; 3.946      ;
; 7.324 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.258     ; 3.946      ;
; 7.329 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.381     ; 3.806      ;
; 7.329 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.379     ; 3.808      ;
; 7.329 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.954      ;
; 7.330 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.371     ; 3.815      ;
; 7.330 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.371     ; 3.815      ;
; 7.330 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.371     ; 3.815      ;
; 7.332 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.372     ; 3.812      ;
; 7.332 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.373     ; 3.811      ;
; 7.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.254     ; 3.933      ;
; 7.341 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.252     ; 3.935      ;
; 7.342 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.244     ; 3.942      ;
; 7.342 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.244     ; 3.942      ;
; 7.342 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.244     ; 3.942      ;
; 7.344 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.246     ; 3.938      ;
; 7.344 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.245     ; 3.939      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.990      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.350 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.190     ; 3.988      ;
; 7.378 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.078      ;
; 7.378 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.078      ;
; 7.378 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.078      ;
; 7.378 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.078      ;
; 7.378 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 4.078      ;
; 7.385 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 4.069      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.387 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.065      ;
; 7.423 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.029      ;
; 7.423 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.206     ; 4.029      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.740      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.740      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.740      ;
; 7.600 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 3.740      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.202     ; 3.586      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.203     ; 3.585      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.205     ; 3.583      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
; 7.870 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.204     ; 3.584      ;
+-------+------------------------+----------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                   ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.411 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 4.074      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.605      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.886 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.175     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.604      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_clk_out_reg               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.173     ; 3.599      ;
; 7.887 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.174     ; 3.598      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.603      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.168     ; 3.603      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.591      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.591      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.180     ; 3.591      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.606      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.165     ; 3.606      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.607      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.607      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 3.607      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.604      ;
; 7.888 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.602      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.889 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.169     ; 3.601      ;
; 7.897 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[0]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.595      ;
; 7.897 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[1]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.595      ;
; 7.897 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer2_reg[2]                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.167     ; 3.595      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                           ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.484 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.707      ;
; 12.484 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.707      ;
; 12.484 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.707      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.706      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 4.705      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.706      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 4.705      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.212     ; 4.705      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.706      ;
; 12.485 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.211     ; 4.706      ;
; 12.511 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.258     ; 4.633      ;
; 12.513 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.257     ; 4.632      ;
; 12.516 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.250     ; 4.636      ;
; 12.516 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.250     ; 4.636      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.217     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.033 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 4.283      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.034 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.209     ; 4.289      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
; 13.036 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.202     ; 4.294      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.486 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.533      ; 4.425      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.476 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.452      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
; -0.475 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 4.550      ; 4.453      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                          ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.264 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.652      ; 3.353      ;
; 0.267 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.653      ; 3.357      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.524 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.652      ; 3.496      ;
; 0.527 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.653      ; 3.500      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                        ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.343 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.695      ; 3.361      ;
; 2.343 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.695      ; 3.361      ;
; 2.343 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.695      ; 3.361      ;
; 2.366 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.656      ; 3.345      ;
; 2.597 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.695      ; 3.504      ;
; 2.597 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.695      ; 3.504      ;
; 2.597 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.695      ; 3.504      ;
; 2.620 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.656      ; 3.488      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.348      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[4]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.348      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.348      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.206      ; 3.343      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.347      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.206      ; 3.343      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.206      ; 3.343      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.347      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.347      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.214      ; 3.351      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.347      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.204      ; 3.341      ;
; 2.814 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.209      ; 3.346      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.348      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.348      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.202      ; 3.340      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.207      ; 3.345      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.348      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.207      ; 3.345      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.210      ; 3.348      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.208      ; 3.346      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[14]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.208      ; 3.346      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.208      ; 3.346      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.208      ; 3.346      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.207      ; 3.345      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
; 2.815 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24]          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.211      ; 3.349      ;
+-------+--------------------------------------------------------------------------------------+----------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.870 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.366      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.368      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.363      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.363      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.368      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.368      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.363      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.364      ;
; 2.871 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.363      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.371      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.371      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.369      ;
; 2.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.371      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.371      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.371      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.369      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.370      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.175      ; 3.372      ;
; 2.876 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.371      ;
; 3.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.195      ; 3.512      ;
; 3.082 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.195      ; 3.512      ;
; 3.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 3.512      ;
; 3.083 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.194      ; 3.512      ;
; 3.272 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.765      ;
; 3.272 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.172      ; 3.765      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.805      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.311 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.171      ; 3.803      ;
; 3.329 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.826      ;
; 3.329 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.826      ;
; 3.329 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.826      ;
; 3.329 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.176      ; 3.826      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                           ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.193      ; 3.901      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.386 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.190      ; 3.898      ;
; 3.387 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.387 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.191      ; 3.900      ;
; 3.394 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.181      ; 3.897      ;
; 3.394 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.181      ; 3.897      ;
; 3.394 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.181      ; 3.897      ;
; 3.394 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.181      ; 3.897      ;
; 3.394 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.181      ; 3.897      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.416 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.906      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.417 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.168      ; 3.907      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.418 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.176      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
; 3.419 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.175      ; 3.916      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.570 ; 5.790        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.571 ; 5.791        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.575 ; 5.795        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.576 ; 5.796        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.667 ; 5.825        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[8]                   ;
; 5.668 ; 5.826        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.668 ; 5.826        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.696 ; 5.840        ; 0.144          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.781 ; 5.905        ; 0.124          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.840 ; 5.840        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.905 ; 5.905        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                            ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                          ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ;
; 8.507 ; 8.727        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ;
; 8.508 ; 8.728        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ;
; 8.511 ; 8.731        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ;
; 8.512 ; 8.732        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                    ;
; 8.512 ; 8.732        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ;
; 8.512 ; 8.732        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ;
; 8.512 ; 8.732        ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.346  ; 10.376       ; 1.030          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                              ;
; 9.425  ; 10.455       ; 1.030          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                              ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001                             ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                             ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                             ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                             ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                     ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00                                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                     ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq                                                 ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketCheckPreamble:u_sendPacketCheckPreamble|sendPacketCPReady                 ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000              ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100              ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101              ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110              ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]                         ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]                          ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]                            ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]                            ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]                            ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]                            ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]                            ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|TxBitsOut[1]~_Duplicate_1   ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[0]           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutIndex[1]           ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|bufferOutStMachCurrState.10 ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|decBufferCnt                ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|fullSpeedTick               ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[0]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[1]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[2]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[3]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|i[4]                        ;
; 10.113 ; 10.333       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|writeUSBWireData:u_writeUSBWireData|lowSpeedTick                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.10                                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.001                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.010                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.011                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.100                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.101                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.110                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|CurrState_drctCntl.111                                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]                                       ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortReq                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortWEn                                           ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.00001                                      ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[0]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[1]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[2]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[3]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[4]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[5]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[6]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|RXWaitCount[7]                        ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000000          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000001          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000010          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000111          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001000          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001010          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001101          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.001111          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010011          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.010100          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011100          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011101          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011110          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011111          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.100011          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101001          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110001          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110100          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.111000          ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[0]                  ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortCtrl[1]                  ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[2]                  ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortData[3]                  ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|SIEPortTxRdy                    ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[0]                ;
; 10.114 ; 10.334       ; 0.220          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|TxByteOutCtrl[1]                ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.187 ; 17.588       ; 0.401          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.233 ; 17.634       ; 0.401          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]      ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]      ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7] ;
; 17.291 ; 17.511       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]          ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]            ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]            ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]            ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]       ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]       ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]       ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]      ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3] ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[1]        ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]        ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]         ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]         ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]   ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]    ;
; 17.292 ; 17.512       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]    ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]                                                                                                                                               ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ;
; 17.295 ; 17.515       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ;
; 17.298 ; 17.518       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]        ;
; 17.303 ; 17.523       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[1]                                                                                                         ;
; 17.303 ; 17.523       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                         ;
; 17.303 ; 17.523       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[1]                                                                                                              ;
; 17.303 ; 17.523       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                              ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]      ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]          ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]          ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]     ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]      ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]      ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]         ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]    ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                   ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                   ;
; 17.310 ; 17.530       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                   ;
; 17.315 ; 17.535       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[2]                                                                                             ;
; 17.315 ; 17.535       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposp3_snap_reg[3]                                                                                             ;
; 17.315 ; 17.535       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[1][0]                                                                   ;
; 17.315 ; 17.535       ; 0.220          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm0_delay|shift_reg[2][0]                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                        ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.589 ; 17.589       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.590 ; 17.590       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.590 ; 17.590       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.590 ; 17.590       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.590 ; 17.590       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.590 ; 17.590       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.590 ; 17.590       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.651 ; 17.651       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.651 ; 17.651       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                            ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.483 ; 99.785       ; 10.302         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 89.908 ; 100.210      ; 10.302         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.756 ; 99.944       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.759 ; 99.947       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.761 ; 99.949       ; 0.188          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.785 ; 99.785       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.830 ; 100.050      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.831 ; 100.051      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.832 ; 100.052      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.832 ; 99.832       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.835 ; 100.055      ; 0.220          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.845 ; 99.845       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.858 ; 99.858       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862 ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.896 ; 99.896       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.899 ; 99.899       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.901 ; 99.901       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.925 ; 99.925       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.134 ; 3.241 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.107 ; 3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.116 ; 3.223 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.114 ; 3.221 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.108 ; 3.215 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.117 ; 3.224 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.134 ; 3.241 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.120 ; 3.227 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.119 ; 3.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.109 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.119 ; 3.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.430 ; 8.834 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.568 ; 4.836 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.049 ; 4.321 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.755 ; 5.028 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.737 ; 4.977 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.430 ; 8.834 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.433 ; 7.901 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.613 ; 4.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.554 ; 4.863 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.900 ; 6.015 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.927 ; 6.042 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.433 ; 7.901 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.322 ; 6.584 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.744 ; 6.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.140 ; 4.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.974 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.105 ; -2.212 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.105 ; -2.212 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.105 ; -2.212 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.105 ; -2.212 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.116 ; -2.223 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.126 ; -2.233 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.124 ; -2.231 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.118 ; -2.225 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.126 ; -2.233 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.144 ; -2.251 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.140 ; -2.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.130 ; -2.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.129 ; -2.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.119 ; -2.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.129 ; -2.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.964 ; -3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.480 ; -3.730 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.964 ; -3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.597 ; -3.819 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.584 ; -3.761 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -4.372 ; -4.465 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -3.451 ; -3.701 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.508 ; -3.701 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.451 ; -3.731 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.695 ; -4.779 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -4.723 ; -4.790 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.494 ; -3.711 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.154 ; -5.397 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.605 ; -4.904 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -3.069 ; -3.212 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.151 ; -0.261 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.285 ; 3.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.212 ; 2.923 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.202 ; 2.913 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.180 ; 2.891 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.189 ; 2.900 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.198 ; 2.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.285 ; 3.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.199 ; 2.910 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.209 ; 2.920 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.212 ; 2.923 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.299 ; 3.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.213 ; 2.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.299 ; 3.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.311 ; 3.854 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.223 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.354 ; 3.899 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.499 ; 3.188 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.499 ; 3.188 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.499 ; 3.188 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.354 ; 3.899 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.344 ; 3.889 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.274 ; 2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.398 ; 3.101 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.410 ; 3.113 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.346 ; 3.891 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.504 ; 3.193 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.494 ; 3.183 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.341 ; 3.886 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.485 ; 3.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.495 ; 3.184 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.418 ; 3.705 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.250 ; 3.482 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.418 ; 3.705 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.223 ; 2.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.234 ; 2.945 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.831 ; 8.021 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.169 ; 4.033 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.642 ; 4.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.580 ; 7.812 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.559 ; 3.683 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.693 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.449 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.059 ; 5.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.477 ; 2.440 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.051 ; 5.392 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.277 ; 2.220 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.059 ; 5.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.951 ; 5.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.951 ; 5.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.191 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.201 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.191 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.940 ; 5.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.181 ; 2.057 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.169 ; 2.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.179 ; 2.055 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.181 ; 2.057 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.171 ; 2.047 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.180 ; 2.056 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.324 ; 2.040 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.355 ; 2.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.345 ; 2.061 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.345 ; 2.061 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.345 ; 2.061 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.324 ; 2.040 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.332 ; 2.048 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.342 ; 2.058 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.475 ; 3.019 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.343 ; 2.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.353 ; 2.069 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.355 ; 2.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.357 ; 2.073 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.357 ; 2.073 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.488 ; 3.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.500 ; 3.044 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.367 ; 2.083 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.466 ; 1.262 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.641 ; 2.336 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.641 ; 2.336 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.641 ; 2.336 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.545 ; 3.091 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.536 ; 3.082 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.466 ; 1.262 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.541 ; 2.250 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.552 ; 2.261 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.647 ; 2.342 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.538 ; 3.084 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.647 ; 2.342 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.647 ; 2.342 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.637 ; 2.332 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.533 ; 3.079 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.628 ; 2.323 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.638 ; 2.333 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.392 ; 2.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.392 ; 2.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.553 ; 2.836 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.367 ; 2.083 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.377 ; 2.093 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.917 ; 7.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.298 ; 3.167 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.739 ; 3.540 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.670 ; 6.905 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.696 ; 2.818 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.928 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.688 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.469 ; 1.413 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.669 ; 1.633 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.243 ; 4.585 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.469 ; 1.413 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.251 ; 4.593 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.380 ; 1.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.141 ; 4.428 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.380 ; 1.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.390 ; 1.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.380 ; 1.257 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.130 ; 4.417 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.359 ; 1.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.359 ; 1.236 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.369 ; 1.246 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.370 ; 1.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.360 ; 1.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.370 ; 1.247 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 3.501 ; 3.378 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.461 ; 2.461 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.232 ; 3.232 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.232 ; 3.232 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.232 ; 3.232 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.657 ; 3.657 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.005 ; 4.005 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.389 ; 4.389 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.459 ; 4.459 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.421 ; 4.421 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.238 ; 3.238 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.865 ; 2.865 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.471 ; 2.471 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.471 ; 2.471 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.461 ; 2.461 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.824 ; 2.824 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.814 ; 2.814 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.824 ; 2.824 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.296 ; 3.912 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.361 ; 5.977 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 6.361 ; 5.977 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.141 ; 1.170 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.880 ; 1.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.880 ; 1.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.880 ; 1.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.288 ; 2.317 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.623 ; 2.652 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.991 ; 3.020 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.059 ; 3.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.023 ; 3.052 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.886 ; 1.915 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.529 ; 1.558 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.151 ; 1.180 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.151 ; 1.180 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.141 ; 1.170 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.489 ; 1.518 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.479 ; 1.508 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.489 ; 1.518 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.311 ; 2.943 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.647 ; 5.279 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.647 ; 5.279 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.945     ; 3.185     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.945     ; 3.185     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.945     ; 3.185     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.342     ; 3.582     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.695     ; 3.935     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.046     ; 4.286     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.100     ; 4.340     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.085     ; 4.325     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.959     ; 3.199     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.614     ; 2.854     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.253     ; 2.493     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.253     ; 2.493     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.243     ; 2.483     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.568     ; 2.808     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.558     ; 2.798     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.568     ; 2.808     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.923     ; 4.307     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.716     ; 6.100     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.716     ; 6.100     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.162     ; 1.162     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.836     ; 1.836     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.836     ; 1.836     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.836     ; 1.836     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.217     ; 2.217     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.556     ; 2.556     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.893     ; 2.893     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.945     ; 2.945     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.931     ; 2.931     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.849     ; 1.849     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.519     ; 1.519     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.172     ; 1.172     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.172     ; 1.172     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.162     ; 1.162     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.474     ; 1.474     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.464     ; 1.464     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.474     ; 1.474     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.953     ; 3.321     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.028     ; 5.396     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.028     ; 5.396     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                                                                   ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                          ; Note                                           ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
; 36.78 MHz  ; 36.78 MHz       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;                                                ;
; 72.92 MHz  ; 40.0 MHz        ; FPGA_CLK                                                                            ; limit due to minimum period restriction (tmin) ;
; 95.39 MHz  ; 95.39 MHz       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;                                                ;
; 110.69 MHz ; 110.69 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;                                                ;
; 143.97 MHz ; 143.97 MHz      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;                                                ;
+------------+-----------------+-------------------------------------------------------------------------------------+------------------------------------------------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -3.721 ; -140.347      ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -1.812 ; -1.812        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.248 ; -41.748       ;
; FPGA_CLK                                                                            ; -0.437 ; -0.437        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.774  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 5.199  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.985 ; -35.916       ;
; FPGA_CLK                                                                            ; -0.511 ; -0.511        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.386  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.404  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.404  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 12.680 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -2.291 ; -20.619       ;
; FPGA_CLK                                                                            ; -0.568 ; -14.742       ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.677  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.808  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 12.845 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.336 ; -8.436        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 0.273  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.088  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.554  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 3.004  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.571  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.716  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.509  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.345  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.220 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.590 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.536 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -3.721 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.319     ; 1.375      ;
; -3.687 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.319     ; 1.341      ;
; -3.487 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.892     ; 1.568      ;
; -3.392 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.327     ; 1.038      ;
; -3.376 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.327     ; 1.022      ;
; -3.373 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.327     ; 1.019      ;
; -3.366 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.327     ; 1.012      ;
; -3.333 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.919     ; 1.387      ;
; -3.333 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.317     ; 0.989      ;
; -3.322 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.919     ; 1.376      ;
; -3.270 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.919     ; 1.324      ;
; -3.184 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.317     ; 0.840      ;
; -3.164 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.317     ; 0.820      ;
; -3.163 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.317     ; 0.819      ;
; -3.162 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.317     ; 0.818      ;
; -3.148 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.326     ; 0.795      ;
; -3.141 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -2.316     ; 0.798      ;
; -2.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 1.067      ;
; -2.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 1.018      ;
; -2.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 1.015      ;
; -2.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.990      ;
; -2.942 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.990      ;
; -2.938 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.991      ;
; -2.793 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.841      ;
; -2.793 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.841      ;
; -2.792 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.840      ;
; -2.771 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.819      ;
; -2.770 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.925     ; 0.818      ;
; -2.767 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.820      ;
; -2.767 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.818      ;
; -2.766 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.817      ;
; -2.765 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.818      ;
; -2.764 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.817      ;
; -2.764 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.817      ;
; -2.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.923     ; 0.795      ;
; -2.744 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.920     ; 0.797      ;
; -2.743 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.922     ; 0.794      ;
; -2.741 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.918     ; 0.796      ;
; -2.727 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.819      ;
; -2.727 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.819      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.818      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.818      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.818      ;
; -2.726 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.818      ;
; -2.724 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.881     ; 0.816      ;
; -2.718 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.894     ; 0.797      ;
; -2.716 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.894     ; 0.795      ;
; 2.153  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.365      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.358  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.142     ; 9.160      ;
; 2.588  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.132     ; 8.940      ;
; 2.588  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.132     ; 8.940      ;
; 2.614  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.130     ; 8.916      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.616  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.913      ;
; 2.638  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.134     ; 8.888      ;
; 2.900  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.629      ;
; 2.900  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.629      ;
; 2.900  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.629      ;
; 2.900  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.629      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.911  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.606      ;
; 2.924  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.593      ;
; 2.924  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.593      ;
; 2.924  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.143     ; 8.593      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.953  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.131     ; 8.576      ;
; 2.988  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.144     ; 8.528      ;
; 2.988  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.144     ; 8.528      ;
; 2.988  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.144     ; 8.528      ;
; 2.994  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.164     ; 8.502      ;
; 3.016  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.159     ; 8.485      ;
; 3.051  ; ram_do_reg[6]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.162     ; 8.447      ;
; 3.074  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.430      ;
; 3.074  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 8.430      ;
; 3.096  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.163     ; 8.401      ;
; 3.135  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 8.370      ;
; 3.139  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Nreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.367      ;
; 3.139  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Zreg                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.154     ; 8.367      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.812 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -1.747     ; 1.315      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.248 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.320      ;
; -1.226 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.298      ;
; -1.224 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.296      ;
; -1.193 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.265      ;
; -1.170 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.242      ;
; -1.155 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.227      ;
; -1.134 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.206      ;
; -1.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.187      ;
; -1.090 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.162      ;
; -1.056 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.120      ;
; -1.045 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.117      ;
; -1.020 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.084      ;
; -1.019 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.083      ;
; -1.014 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.086      ;
; -1.006 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.078      ;
; -1.001 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.174      ; 2.076      ;
; -1.000 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.072      ;
; -0.999 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.172      ; 2.072      ;
; -0.996 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.060      ;
; -0.994 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.066      ;
; -0.992 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.064      ;
; -0.989 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.053      ;
; -0.983 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.055      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.049      ;
; -0.975 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.047      ;
; -0.971 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.043      ;
; -0.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.037      ;
; -0.964 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.172      ; 2.037      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.027      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.034      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.032      ;
; -0.960 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.032      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 2.013      ;
; -0.940 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 2.003      ;
; -0.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.008      ;
; -0.936 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 2.000      ;
; -0.930 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.002      ;
; -0.929 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 2.001      ;
; -0.923 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.162      ; 1.986      ;
; -0.921 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.171      ; 1.993      ;
; -0.917 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.163      ; 1.981      ;
; 5.228  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.761     ; 6.541      ;
; 5.357  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.761     ; 6.412      ;
; 6.843  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 5.271      ;
; 6.948  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.560      ; 7.031      ;
; 7.139  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.558      ; 6.838      ;
; 7.145  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.963      ;
; 7.145  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.963      ;
; 7.153  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 4.961      ;
; 7.237  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.871      ;
; 7.318  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.558      ; 6.659      ;
; 7.360  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.558      ; 6.617      ;
; 7.360  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.748      ;
; 7.375  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.733      ;
; 7.439  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.560      ; 6.540      ;
; 7.446  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.560      ; 6.533      ;
; 7.497  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.611      ;
; 7.505  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 3.558      ; 6.472      ;
; 7.530  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.579      ;
; 7.545  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 4.569      ;
; 7.592  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.516      ;
; 7.593  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.515      ;
; 7.714  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.395      ;
; 7.717  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.392      ;
; 7.720  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 4.394      ;
; 7.798  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.311      ;
; 7.856  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 4.258      ;
; 7.904  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.204      ;
; 7.932  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.177      ;
; 7.945  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.416     ; 4.169      ;
; 7.952  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.422     ; 4.156      ;
; 7.988  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.419     ; 4.123      ;
; 8.067  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.421     ; 4.042      ;
; 8.314  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.419     ; 3.797      ;
; 8.592  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.420     ; 3.518      ;
; 9.140  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.121     ; 1.157      ;
; 9.293  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.121     ; 1.004      ;
; 10.350 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 10.412     ;
; 10.351 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 10.411     ;
; 10.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.073     ; 10.346     ;
; 10.562 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.189     ;
; 10.563 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.188     ;
; 10.583 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.168     ;
; 10.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.167     ;
; 10.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.123     ;
; 10.648 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.103     ;
; 10.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.102     ;
; 10.649 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.102     ;
; 10.714 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 10.037     ;
; 10.786 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.965      ;
; 10.787 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.964      ;
; 10.818 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.933      ;
; 10.819 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.932      ;
; 10.852 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.899      ;
; 10.884 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.867      ;
; 10.890 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.861      ;
; 10.891 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.860      ;
; 10.956 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.795      ;
; 11.156 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.595      ;
; 11.157 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.084     ; 9.594      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.437  ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.184      ; 4.389      ;
; 93.143  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.983     ; 5.876      ;
; 96.044  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.787      ; 1.996      ;
; 196.788 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 3.144      ;
; 196.827 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 3.105      ;
; 196.874 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 3.058      ;
; 196.913 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 3.019      ;
; 196.914 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 3.018      ;
; 196.952 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.980      ;
; 196.953 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.979      ;
; 196.994 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.938      ;
; 196.996 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.936      ;
; 197.000 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.932      ;
; 197.039 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.893      ;
; 197.040 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.892      ;
; 197.040 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.892      ;
; 197.078 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.854      ;
; 197.079 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.853      ;
; 197.079 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.853      ;
; 197.107 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.825      ;
; 197.120 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.812      ;
; 197.122 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.810      ;
; 197.126 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.806      ;
; 197.129 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.803      ;
; 197.165 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.767      ;
; 197.165 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.767      ;
; 197.166 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.766      ;
; 197.166 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.766      ;
; 197.204 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.728      ;
; 197.204 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.728      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.727      ;
; 197.205 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.727      ;
; 197.233 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.699      ;
; 197.244 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.688      ;
; 197.246 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.686      ;
; 197.248 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.684      ;
; 197.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.680      ;
; 197.252 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.680      ;
; 197.255 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.677      ;
; 197.291 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.641      ;
; 197.291 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.641      ;
; 197.292 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.640      ;
; 197.292 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.640      ;
; 197.294 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.638      ;
; 197.330 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.602      ;
; 197.330 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.602      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.601      ;
; 197.331 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.601      ;
; 197.333 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.599      ;
; 197.359 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.573      ;
; 197.370 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.562      ;
; 197.372 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.560      ;
; 197.374 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.558      ;
; 197.375 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.557      ;
; 197.378 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.554      ;
; 197.378 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.554      ;
; 197.378 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.554      ;
; 197.381 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.551      ;
; 197.417 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.515      ;
; 197.417 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.515      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.514      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.514      ;
; 197.418 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.514      ;
; 197.420 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.512      ;
; 197.456 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.476      ;
; 197.456 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.476      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.475      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.475      ;
; 197.457 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.475      ;
; 197.459 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.473      ;
; 197.485 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.447      ;
; 197.496 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.436      ;
; 197.498 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.434      ;
; 197.500 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.432      ;
; 197.501 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.431      ;
; 197.501 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.431      ;
; 197.503 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.429      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.428      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.428      ;
; 197.504 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.428      ;
; 197.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.425      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.388      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.389      ;
; 197.543 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.389      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.388      ;
; 197.544 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.388      ;
; 197.546 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.385      ;
; 197.546 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.386      ;
; 197.582 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.350      ;
; 197.582 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.350      ;
; 197.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.349      ;
; 197.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.349      ;
; 197.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.349      ;
; 197.585 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.346      ;
; 197.585 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.347      ;
; 197.611 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.321      ;
; 197.622 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.310      ;
; 197.624 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.308      ;
; 197.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.070     ; 2.307      ;
; 197.625 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.071     ; 2.306      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.774 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 4.754      ;
; 0.788 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 4.745      ;
; 0.887 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 4.641      ;
; 1.017 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 4.523      ;
; 1.107 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 4.420      ;
; 1.107 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 4.420      ;
; 1.130 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 4.410      ;
; 1.154 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 4.374      ;
; 1.232 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 4.295      ;
; 1.232 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.132     ; 4.295      ;
; 1.279 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 4.249      ;
; 1.335 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.195      ;
; 1.460 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 4.070      ;
; 1.481 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 4.047      ;
; 1.524 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 4.018      ;
; 1.606 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 3.922      ;
; 1.609 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 3.932      ;
; 1.636 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.904      ;
; 1.636 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.904      ;
; 1.636 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.904      ;
; 1.636 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.904      ;
; 1.734 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 3.807      ;
; 1.761 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.779      ;
; 1.761 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.779      ;
; 1.761 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.779      ;
; 1.761 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.779      ;
; 1.868 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 3.667      ;
; 1.906 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.634      ;
; 2.010 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.111     ; 3.538      ;
; 2.031 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 3.509      ;
; 2.057 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.136     ; 3.466      ;
; 2.126 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.406      ;
; 2.165 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 3.380      ;
; 2.181 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.344      ;
; 2.212 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 3.323      ;
; 2.274 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 3.259      ;
; 2.294 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.137     ; 3.228      ;
; 2.296 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.111     ; 3.252      ;
; 2.308 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.350      ;
; 2.308 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.350      ;
; 2.309 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 3.232      ;
; 2.310 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.348      ;
; 2.310 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.348      ;
; 2.311 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.347      ;
; 2.311 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.347      ;
; 2.313 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.345      ;
; 2.313 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.127     ; 3.345      ;
; 2.434 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.118     ; 3.107      ;
; 2.439 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 3.096      ;
; 2.442 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.209      ;
; 2.442 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.209      ;
; 2.444 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.207      ;
; 2.444 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.207      ;
; 2.445 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.206      ;
; 2.445 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.206      ;
; 2.447 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.204      ;
; 2.447 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 3.204      ;
; 2.456 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.080      ;
; 2.469 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.193      ;
; 2.518 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 3.015      ;
; 2.525 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 3.136      ;
; 2.553 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 2.992      ;
; 2.594 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -1.746     ; 1.316      ;
; 2.644 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 3.018      ;
; 2.652 ; SDRAM_ADDR[2]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.892      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.679 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.133     ; 2.973      ;
; 2.698 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.953      ;
; 2.698 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.953      ;
; 2.698 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.953      ;
; 2.698 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.134     ; 2.953      ;
; 2.721 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.935      ;
; 2.740 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.921      ;
; 2.741 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.920      ;
; 2.748 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 2.917      ;
; 2.749 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 2.916      ;
; 2.786 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.869      ;
; 2.813 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.731      ;
; 2.891 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.763      ;
; 2.891 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.763      ;
; 2.892 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.762      ;
; 2.918 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.739      ;
; 2.931 ; SDRAM_ADDR[10]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 2.603      ;
; 2.947 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.597      ;
; 2.950 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.115     ; 2.594      ;
; 3.008 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 2.655      ;
; 3.011 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 2.652      ;
; 3.020 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.637      ;
; 3.020 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.637      ;
; 3.031 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.128     ; 2.626      ;
; 3.067 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.588      ;
; 3.067 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.588      ;
; 3.127 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.529      ;
; 3.127 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.529      ;
; 3.127 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.529      ;
; 3.127 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 2.529      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 5.199  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -1.746     ; 1.648      ;
; 7.934  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.223     ; 9.250      ;
; 8.245  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.182     ; 8.980      ;
; 8.374  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 8.852      ;
; 8.415  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 8.812      ;
; 8.456  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 8.733      ;
; 8.492  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.182     ; 8.733      ;
; 8.522  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 8.704      ;
; 8.525  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 8.701      ;
; 8.531  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 8.696      ;
; 8.587  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 8.671      ;
; 8.800  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.225     ; 8.382      ;
; 8.888  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.181     ; 8.338      ;
; 9.002  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 8.256      ;
; 9.006  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 8.252      ;
; 9.277  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 7.981      ;
; 9.280  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.976      ;
; 9.337  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.963      ;
; 9.383  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.916      ;
; 9.407  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 7.851      ;
; 9.409  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[2]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.184     ; 7.814      ;
; 9.440  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.859      ;
; 9.463  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.793      ;
; 9.494  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.806      ;
; 9.496  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.760      ;
; 9.520  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.779      ;
; 9.559  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 7.662      ;
; 9.590  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.710      ;
; 9.625  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.675      ;
; 9.681  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.620      ;
; 9.681  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.619      ;
; 9.688  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 7.575      ;
; 9.688  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.611      ;
; 9.704  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.552      ;
; 9.759  ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 7.462      ;
; 9.771  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.530      ;
; 9.782  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.518      ;
; 9.856  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.444      ;
; 9.862  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 7.401      ;
; 9.865  ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.435      ;
; 10.003 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.296      ;
; 10.003 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.298      ;
; 10.019 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.282      ;
; 10.026 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.273      ;
; 10.043 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.213      ;
; 10.045 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 7.144      ;
; 10.048 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.251      ;
; 10.050 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.251      ;
; 10.058 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 7.205      ;
; 10.065 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.236      ;
; 10.076 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.224      ;
; 10.092 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.151     ; 7.164      ;
; 10.116 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 7.147      ;
; 10.128 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.172      ;
; 10.185 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 7.114      ;
; 10.186 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 7.077      ;
; 10.236 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 7.065      ;
; 10.263 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.037      ;
; 10.274 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 7.026      ;
; 10.321 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 6.980      ;
; 10.324 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 6.975      ;
; 10.359 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.941      ;
; 10.366 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.934      ;
; 10.395 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 6.904      ;
; 10.468 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.832      ;
; 10.473 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.827      ;
; 10.551 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.749      ;
; 10.612 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 6.689      ;
; 10.615 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 6.686      ;
; 10.653 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.647      ;
; 10.684 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.616      ;
; 10.701 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 6.600      ;
; 10.706 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 6.593      ;
; 10.737 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.563      ;
; 10.834 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 6.467      ;
; 10.878 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.149     ; 6.380      ;
; 10.890 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.403     ; 6.240      ;
; 10.925 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 6.338      ;
; 10.936 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 6.327      ;
; 11.087 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 6.141      ;
; 11.102 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 6.161      ;
; 11.127 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 6.136      ;
; 11.155 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.405     ; 5.973      ;
; 11.225 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 6.075      ;
; 11.302 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 5.961      ;
; 11.308 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 5.955      ;
; 11.343 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.412     ; 5.778      ;
; 11.357 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 5.906      ;
; 11.371 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 5.928      ;
; 11.389 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.403     ; 5.741      ;
; 11.416 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 5.847      ;
; 11.482 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.412     ; 5.639      ;
; 11.488 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.405     ; 5.640      ;
; 11.539 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 5.761      ;
; 11.542 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 5.759      ;
; 11.594 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.179     ; 5.634      ;
; 11.654 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.144     ; 5.609      ;
; 11.679 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 5.620      ;
; 11.687 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.403     ; 5.443      ;
; 11.734 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.098     ; 5.575      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.985 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.644      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.643      ;
; -0.977 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.652      ;
; -0.965 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.664      ;
; -0.963 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.665      ;
; -0.962 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.658      ;
; -0.952 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.668      ;
; -0.951 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.678      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.679      ;
; -0.950 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.670      ;
; -0.949 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.671      ;
; -0.946 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.683      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.683      ;
; -0.945 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.683      ;
; -0.933 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.687      ;
; -0.932 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.696      ;
; -0.922 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.706      ;
; -0.919 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.710      ;
; -0.910 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.710      ;
; -0.908 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.721      ;
; -0.905 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.723      ;
; -0.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.729      ;
; -0.895 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.734      ;
; -0.883 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.745      ;
; -0.877 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.325      ; 1.751      ;
; -0.875 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.745      ;
; -0.863 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.766      ;
; -0.857 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.763      ;
; -0.849 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.780      ;
; -0.814 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.806      ;
; -0.804 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.327      ; 1.826      ;
; -0.791 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.838      ;
; -0.787 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.842      ;
; -0.770 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.317      ; 1.850      ;
; -0.753 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.876      ;
; -0.753 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.876      ;
; -0.730 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.899      ;
; -0.729 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.900      ;
; -0.719 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.910      ;
; -0.717 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.912      ;
; -0.705 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.326      ; 1.924      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                            ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|doUpdateCRC                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|ready                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|rstCRC                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[1]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[2]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|i[3]                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5En                    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC5_8Bit                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|loopEnd[0]                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|doUpdateCRC                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|ready                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxDataOutWEn              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[1]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrlOut[0]              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|data[7]                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:RxUpdateCRC5|data[7]                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00100                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00111                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXPacketRdy                                           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01111                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.669      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.511 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.977      ; 3.827      ;
; 0.469  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.735      ;
; 0.470  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.736      ;
; 0.625  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.891      ;
; 0.693  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.959      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.695  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.961      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.696  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.962      ;
; 0.697  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.963      ;
; 0.698  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.964      ;
; 0.700  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.966      ;
; 0.708  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.974      ;
; 0.710  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.976      ;
; 0.710  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.976      ;
; 0.710  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.976      ;
; 0.711  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.977      ;
; 0.711  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.977      ;
; 0.713  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.979      ;
; 0.714  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.980      ;
; 0.714  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.980      ;
; 0.723  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 0.989      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 0.937  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.203      ;
; 1.014  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.280      ;
; 1.014  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.281      ;
; 1.014  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.280      ;
; 1.014  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.280      ;
; 1.015  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.281      ;
; 1.017  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.017  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.017  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.283      ;
; 1.019  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.019  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.019  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.285      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.020  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.286      ;
; 1.021  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.287      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.296      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.029  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.295      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.030  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.296      ;
; 1.031  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.297      ;
; 1.031  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.297      ;
; 1.032  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.298      ;
; 1.034  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.300      ;
; 1.034  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.300      ;
; 1.035  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.301      ;
; 1.035  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.301      ;
; 1.044  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.310      ;
; 1.047  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.313      ;
; 1.048  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.314      ;
; 1.048  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.314      ;
; 1.114  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.380      ;
; 1.115  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.381      ;
; 1.115  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.381      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.383      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.382      ;
; 1.116  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.382      ;
; 1.117  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.383      ;
; 1.118  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.384      ;
; 1.123  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.389      ;
; 1.128  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.394      ;
; 1.129  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.395      ;
; 1.130  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.396      ;
; 1.135  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.402      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.403      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.402      ;
; 1.136  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.402      ;
; 1.137  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.403      ;
; 1.139  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.139  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.139  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.405      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.072      ; 1.408      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
; 1.141  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.071      ; 1.407      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                ; To Node                                                                                                                                                                                  ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.386 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.386 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.088      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[6]                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|count_reg[1]                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[7]                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[31]                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[7] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[6] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[5] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[4] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[3] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[2] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[1] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|low_addressa[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.ready                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|busy                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|busy                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                    ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load_sp2                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                     ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_fetch                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_reset_n_reg                                                                                                                                                                        ; sdram_reset_n_reg                                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[54]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[52]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[38]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[35]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; paddle_mode_reg                                                                                                                                                                          ; paddle_mode_reg                                                                                                                                                                          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[53]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[73]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[28]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                           ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[20]                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[0]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[2]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[3]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig_reg[1]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|busy                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c0_write_reg                                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.ready                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|state.command                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|stretch                                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[7]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[5]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[5]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[1]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|data_rx[1]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|sdram_rdy                     ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_reg                                         ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_request_complete_reg                                ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.419 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.684      ;
; 0.420 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.684      ;
; 0.487 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.752      ;
; 0.494 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.759      ;
; 0.495 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.760      ;
; 0.502 ; seq_reg[10]                                               ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.767      ;
; 0.511 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.776      ;
; 0.601 ; ram_bena_reg[0]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.866      ;
; 0.602 ; ram_bena_reg[1]                                           ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.867      ;
; 0.635 ; seq_reg[9]                                                ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.900      ;
; 0.654 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.919      ;
; 0.679 ; seq_reg[8]                                                ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.944      ;
; 0.687 ; seq_reg[2]                                                ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.952      ;
; 0.687 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.951      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.952      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.953      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.953      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.954      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.954      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.956      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.957      ;
; 0.693 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.957      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.976      ;
; 0.712 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 0.976      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.005      ;
; 0.750 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.015      ;
; 0.784 ; sdram_ctrl:sdram_controller|r_refr_act                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.049      ;
; 0.837 ; seq_reg[3]                                                ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.102      ;
; 0.849 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.114      ;
; 0.899 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.163      ;
; 0.935 ; sdram_ctrl:sdram_controller|r_rd_act                      ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.200      ;
; 0.968 ; sdram_request_reg                                         ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.233      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.272      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.272      ;
; 1.009 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.273      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.011 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.275      ;
; 1.013 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.277      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.278      ;
; 1.014 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.278      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.287      ;
; 1.023 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.287      ;
; 1.025 ; seq_reg[4]                                                ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.286      ;
; 1.027 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.291      ;
; 1.027 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.291      ;
; 1.027 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.291      ;
; 1.032 ; seq_reg[4]                                                ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.295      ;
; 1.042 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.068      ; 1.305      ;
; 1.082 ; seq_reg[1]                                                ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.347      ;
; 1.103 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.367      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.373      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.373      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.394      ;
; 1.131 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.395      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.397      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.397      ;
; 1.133 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.397      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.237      ; 1.568      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.400      ;
; 1.136 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.400      ;
; 1.142 ; seq_reg[1]                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.407      ;
; 1.145 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.409      ;
; 1.149 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.414      ;
; 1.149 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.413      ;
; 1.149 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.413      ;
; 1.149 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.413      ;
; 1.150 ; seq_reg[9]                                                ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.415      ;
; 1.152 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.066      ; 1.413      ;
; 1.153 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.419      ;
; 1.160 ; seq_reg[7]                                                ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.425      ;
; 1.173 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.437      ;
; 1.187 ; sdram_ctrl:sdram_controller|r_refr_req                    ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.453      ;
; 1.189 ; seq_reg[0]                                                ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.454      ;
; 1.192 ; seq_reg[11]                                               ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.457      ;
; 1.203 ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.242      ; 1.640      ;
; 1.206 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.023      ; 1.341      ;
; 1.206 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.023      ; 1.341      ;
; 1.206 ; sdram_ctrl:sdram_controller|r_wr_act                      ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.023      ; 1.341      ;
; 1.209 ; seq_reg[11]                                               ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.474      ;
; 1.216 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.483      ;
; 1.217 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.484      ;
; 1.218 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.483      ;
; 1.219 ; sdram_ctrl:sdram_controller|r_psel[0]                     ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.486      ;
; 1.225 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.489      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.069      ; 1.495      ;
+-------+-----------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                     ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                        ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                              ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.404 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                            ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.669      ;
; 0.419 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.684      ;
; 0.469 ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                                             ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.734      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.471 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.736      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.736      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.472 ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                    ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.738      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.473 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.737      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.738      ;
; 0.474 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.739      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.740      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.740      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.739      ;
; 0.475 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.739      ;
; 0.476 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.740      ;
; 0.522 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.523      ; 1.385      ;
; 0.611 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.876      ;
; 0.611 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.071      ; 0.877      ;
; 0.612 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.877      ;
; 0.624 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.889      ;
; 0.624 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.889      ;
; 0.626 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.891      ;
; 0.627 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.891      ;
; 0.627 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.891      ;
; 0.628 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.892      ;
; 0.646 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.911      ;
; 0.646 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.911      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.911      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.647 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.912      ;
; 0.648 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.913      ;
; 0.648 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.913      ;
; 0.648 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.070      ; 0.913      ;
; 0.648 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.069      ; 0.912      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.680 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -1.499     ; 1.072      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.179      ; 3.371      ;
; -2.291 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 1.183      ; 3.375      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.179      ; 3.248      ;
; -2.103 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 1.183      ; 3.252      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                                ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.568 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.180      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.567 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.181      ; 4.516      ;
; -0.555 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 3.168      ; 4.491      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                           ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                  ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.676      ;
; 7.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 3.675      ;
; 7.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.181     ; 3.675      ;
; 7.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.676      ;
; 7.677 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.676      ;
; 7.678 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.677      ;
; 7.684 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.355     ; 3.483      ;
; 7.686 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.347     ; 3.489      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.349     ; 3.485      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.483      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.483      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.351     ; 3.483      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.349     ; 3.485      ;
; 7.688 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.349     ; 3.485      ;
; 7.693 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.338     ; 3.491      ;
; 7.701 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.665      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.702 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.168     ; 3.663      ;
; 7.705 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.347     ; 3.470      ;
; 7.706 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.338     ; 3.478      ;
; 7.706 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.344     ; 3.472      ;
; 7.706 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.340     ; 3.476      ;
; 7.709 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.335     ; 3.478      ;
; 7.709 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.335     ; 3.478      ;
; 7.709 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.335     ; 3.478      ;
; 7.721 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.235     ; 3.577      ;
; 7.723 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 3.583      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.577      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.577      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.231     ; 3.577      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.579      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.579      ;
; 7.725 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.229     ; 3.579      ;
; 7.730 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.585      ;
; 7.742 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.227     ; 3.564      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.224     ; 3.566      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.220     ; 3.570      ;
; 7.743 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.218     ; 3.572      ;
; 7.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.572      ;
; 7.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.572      ;
; 7.746 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.215     ; 3.572      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.734      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.734      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.734      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.734      ;
; 7.747 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.734      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.180     ; 3.722      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.757 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 3.719      ;
; 7.796 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.684      ;
; 7.796 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 3.684      ;
; 7.933 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.433      ;
; 7.933 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.167     ; 3.433      ;
; 7.934 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.433      ;
; 7.934 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.166     ; 3.433      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.204 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.279      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.277      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.277      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.177     ; 3.277      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.178     ; 3.276      ;
; 8.205 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.176     ; 3.278      ;
+-------+------------------------+----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                    ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 7.808 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.696      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.259      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.151     ; 3.259      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.250 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.253      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.251      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.251      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.251      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.251      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.251      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_clk_out_reg               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.252      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.252      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.252      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.252      ;
; 8.252 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.252      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.156     ; 3.251      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.157     ; 3.250      ;
; 8.253 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.155     ; 3.252      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.256      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.149     ; 3.256      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.259      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.146     ; 3.259      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.255 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.255      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.244      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.244      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.160     ; 3.244      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.259      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.150     ; 3.254      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.259      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.145     ; 3.259      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.256 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.148     ; 3.256      ;
; 8.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[0]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.147     ; 3.253      ;
; 8.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[5]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.248      ;
; 8.260 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|count[6]                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.152     ; 3.248      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 4.373      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.188     ; 4.374      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.188     ; 4.374      ;
; 12.845 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.188     ; 4.374      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 4.372      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.188     ; 4.373      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 4.372      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.189     ; 4.372      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 4.374      ;
; 12.846 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.187     ; 4.374      ;
; 12.888 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.232     ; 4.287      ;
; 12.889 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.230     ; 4.288      ;
; 12.893 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.225     ; 4.289      ;
; 12.893 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.225     ; 4.289      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.371 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.194     ; 3.967      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.372 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.193     ; 3.968      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.375 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.186     ; 3.972      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
; 13.377 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.180     ; 3.976      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.336 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.960      ; 3.985      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.973      ; 4.010      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
; -0.324 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 3.974      ; 4.011      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.332      ; 3.025      ;
; 0.273 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 2.336      ; 3.029      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.332      ; 3.157      ;
; 0.522 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 2.336      ; 3.161      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.088 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.637      ; 3.031      ;
; 2.088 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.637      ; 3.031      ;
; 2.088 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.637      ; 3.031      ;
; 2.117 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.595      ; 3.018      ;
; 2.331 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 3.163      ;
; 2.331 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 3.163      ;
; 2.331 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.637      ; 3.163      ;
; 2.360 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.595      ; 3.150      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 3.015      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 3.015      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 3.015      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.183      ; 3.018      ;
; 2.529 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.178      ; 3.013      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.017      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.017      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.181      ; 3.017      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.187      ; 3.023      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[30] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[31] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.185      ; 3.021      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 3.016      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.180      ; 3.016      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.173      ; 3.009      ;
; 2.530 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.182      ; 3.018      ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 2.554 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.014      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.009      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.009      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.014      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.014      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.009      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.152      ; 3.010      ;
; 2.554 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.151      ; 3.009      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.017      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.017      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.017      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.017      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.155      ; 3.014      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.015      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.013      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.016      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.018      ;
; 2.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.017      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.157      ; 3.018      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.158      ; 3.019      ;
; 2.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.141      ;
; 2.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.142      ;
; 2.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.174      ; 3.142      ;
; 2.747 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.173      ; 3.141      ;
; 2.906 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.364      ;
; 2.906 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.364      ;
; 2.943 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.154      ; 3.401      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.944 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.150      ; 3.398      ;
; 2.957 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.417      ;
; 2.957 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.417      ;
; 2.957 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.417      ;
; 2.957 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.156      ; 3.417      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.004 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.170      ; 3.479      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.171      ; 3.480      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.004 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.169      ; 3.478      ;
; 3.010 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.475      ;
; 3.010 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.475      ;
; 3.010 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.475      ;
; 3.010 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.475      ;
; 3.010 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.160      ; 3.475      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.149      ; 3.486      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.155      ; 3.492      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 3.491      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 3.491      ;
; 3.032 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.154      ; 3.491      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.571 ; 5.787        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.572 ; 5.788        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.573 ; 5.789        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.574 ; 5.790        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.677 ; 5.832        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.716 ; 5.842        ; 0.126          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.796 ; 5.905        ; 0.109          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.842 ; 5.842        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.905 ; 5.905        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                             ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                        ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                          ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ;
; 8.509 ; 8.725        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ;
; 8.510 ; 8.726        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; half_scandouble_enable_reg                                                    ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ;
; 8.511 ; 8.727        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                      ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.345  ; 10.355       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                 ;
; 9.466  ; 10.476       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                     ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                   ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                                                     ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.001                                                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.010                                                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.011                                                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.100                                                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|SOFCntlGnt                                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|directCntlGnt                                                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|muxCntl.00                                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|sendPacketGnt                                                        ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[0]                                                       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg[1]                                                       ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                  ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                                                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000                                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110                                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                                                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                                     ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01000                                                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|CurrState_sndPkt.01001                                                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|HCTxPortReq                                                                    ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.000100                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.011011                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101000                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.101101                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIETransmitter:u_SIETransmitter|CurrState_SIETx.110000                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1000                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110                                 ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                                           ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|SIERxWEn                                         ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.00                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.01                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|bufferOutStMachCurrState.10                      ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|readUSBWireData:u_readUSBWireData|noActivityTimeOut                                ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[0]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[10]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[11]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[12]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[13]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[14]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[15]                                            ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[1]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[2]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[7]                                             ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[0]                                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[1]                                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[2]                                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[3]                                               ;
; 10.114 ; 10.330       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC5:TxUpdateCRC5|CRCResult[4]                                               ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[0]                                                                                                                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[1]                                                                                                                                                          ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|areset_state                                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                                                                    ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_init_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                       ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_ena_state                                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reset_state                                                                   ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_ena_state                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_ena_state                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_ena_state                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_ena_state                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                 ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_ena_state                                                  ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate_state                                            ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state                                                    ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[0] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[1] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[2] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[3] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[4] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr13|cntr_ieo:auto_generated|counter_reg_bit[5] ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_counter_state                                        ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_init_state                                           ;
; 10.115 ; 10.331       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                           ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                  ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.220 ; 17.602       ; 0.382          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[0]                                         ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[1]                                         ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[2]                                         ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[3]                                         ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|volume_sum_reg[4]                                         ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[10]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[11]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[12]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[13]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[14]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[15]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[16]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[17]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[18]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[19]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[20]                                              ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[5]                                               ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[6]                                               ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[7]                                               ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[8]                                               ;
; 17.243 ; 17.625       ; 0.382          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer|yadj_reg[9]                                               ;
; 17.269 ; 17.485       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]          ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]            ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]            ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[3]            ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]       ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]       ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]       ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]      ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3] ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[1]        ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[10]        ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[1]         ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]         ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]   ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]    ;
; 17.272 ; 17.488       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]    ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[2]      ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[4]      ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6] ;
; 17.273 ; 17.489       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7] ;
; 17.275 ; 17.491       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]        ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]     ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]      ;
; 17.277 ; 17.493       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]      ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[1]                                                                                                         ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                         ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[1]                                                                                                              ;
; 17.280 ; 17.496       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                              ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ;
; 17.281 ; 17.497       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]                                                                                                                                               ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[7]      ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[14]          ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB[15]          ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[6]         ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]    ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                                                                   ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                   ;
; 17.283 ; 17.499       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                   ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                                                                         ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                                                                         ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                                                                          ;
; 17.320 ; 17.536       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                                                                         ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.590 ; 17.590       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.590 ; 17.590       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.591 ; 17.591       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.591 ; 17.591       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.591 ; 17.591       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.591 ; 17.591       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.591 ; 17.591       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.594 ; 17.594       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.648 ; 17.648       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.649 ; 17.649       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.652 ; 17.652       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                             ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.536 ; 99.636       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.255 ; 100.355      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.636 ; 99.636       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 99.733 ; 99.733       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.741 ; 99.741       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.757 ; 99.941       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.758 ; 99.942       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.831 ; 99.831       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837 ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.839 ; 100.055      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.840 ; 100.056      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.888 ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.890 ; 99.890       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.891 ; 99.891       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.914 ; 99.914       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
+--------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.739 ; 2.846 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.699 ; 2.806 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.712 ; 2.819 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.721 ; 2.828 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.718 ; 2.825 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.714 ; 2.821 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.722 ; 2.829 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.731 ; 2.838 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.739 ; 2.846 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.735 ; 2.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.735 ; 2.842 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.725 ; 2.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.723 ; 2.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.713 ; 2.820 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.723 ; 2.830 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 7.598 ; 8.104 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.995 ; 4.393 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.538 ; 3.891 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.195 ; 4.542 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.184 ; 4.479 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 7.598 ; 8.104 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.591 ; 7.312 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.059 ; 4.363 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.988 ; 4.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.279 ; 5.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.311 ; 5.464 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.591 ; 7.312 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 5.544 ; 5.672 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 4.992 ; 5.221 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.620 ; 3.870 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.728 ; 0.838 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.818 ; -1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.832 ; -1.940 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.841 ; -1.949 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.838 ; -1.946 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.833 ; -1.941 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.842 ; -1.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.851 ; -1.959 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.858 ; -1.966 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.854 ; -1.962 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.854 ; -1.962 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.844 ; -1.952 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.842 ; -1.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.832 ; -1.940 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.842 ; -1.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.570 ; -2.906 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -3.031 ; -3.408 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.570 ; -2.906 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.165 ; -3.460 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.158 ; -3.394 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.934 ; -4.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -3.010 ; -3.356 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -3.079 ; -3.356 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.010 ; -3.407 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -4.203 ; -4.329 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -4.235 ; -4.346 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -3.040 ; -3.380 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -4.510 ; -4.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -3.984 ; -4.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.670 ; -2.906 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.223 ; 2.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.231 ; 2.995 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.240 ; 3.004 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.242 ; 3.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.252 ; 3.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.255 ; 3.019 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.521 ; 4.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.559 ; 4.111 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.490 ; 2.292 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.435 ; 3.192 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.446 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.545 ; 3.288 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.562 ; 4.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.542 ; 3.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.542 ; 3.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.532 ; 3.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.558 ; 4.110 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.524 ; 3.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.534 ; 3.277 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.510 ; 3.857 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.349 ; 3.647 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.510 ; 3.857 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.276 ; 3.040 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.991 ; 7.984 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.358 ; 4.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.803 ; 4.392 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.708 ; 7.780 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.632 ; 3.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.997 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.719 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.273 ; 5.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.693 ; 2.663 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.266 ; 5.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.491 ; 2.441 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.273 ; 5.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.402 ; 2.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.412 ; 2.295 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.402 ; 2.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.151 ; 5.444 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.380 ; 2.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.390 ; 2.273 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.382 ; 2.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.391 ; 2.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.020 ; 3.903 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.470 ; 2.238 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.500 ; 2.268 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.490 ; 2.258 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.470 ; 2.238 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.478 ; 2.246 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.487 ; 2.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.781 ; 3.332 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.488 ; 2.256 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.498 ; 2.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.500 ; 2.268 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.501 ; 2.269 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.501 ; 2.269 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.794 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.806 ; 3.357 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.511 ; 2.279 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.778 ; 1.581 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.783 ; 2.530 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.856 ; 3.409 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.847 ; 3.400 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.778 ; 1.581 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.680 ; 2.441 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.692 ; 2.453 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.791 ; 2.538 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.849 ; 3.402 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.787 ; 2.534 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.787 ; 2.534 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.777 ; 2.524 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.845 ; 3.398 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.769 ; 2.516 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.779 ; 2.526 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.591 ; 2.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.591 ; 2.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.746 ; 3.086 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.511 ; 2.279 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.522 ; 2.290 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.175 ; 7.183 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.585 ; 3.330 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 3.998 ; 3.600 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.897 ; 6.979 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.871 ; 3.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.324 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.050 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.778 ; 1.729 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.980 ; 1.951 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 4.553 ; 4.902 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.778 ; 1.729 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 4.560 ; 4.909 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 4.448 ; 4.742 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.697 ; 1.581 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.687 ; 1.571 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 4.437 ; 4.731 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.666 ; 1.550 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.666 ; 1.550 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.676 ; 1.560 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.678 ; 1.562 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.668 ; 1.552 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.676 ; 1.560 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 3.553 ; 3.437 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.296 ; 2.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.023 ; 3.023 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.023 ; 3.023 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.023 ; 3.023 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.424 ; 3.424 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.754 ; 3.754 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.121 ; 4.121 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.182 ; 4.182 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.144 ; 4.144 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.030 ; 3.030 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.678 ; 2.678 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.306 ; 2.306 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.306 ; 2.306 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.296 ; 2.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.642 ; 2.642 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.632 ; 2.632 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.642 ; 2.642 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.399 ; 4.023 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 6.252 ; 5.876 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 6.252 ; 5.876 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.280 ; 1.280 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.977 ; 1.977 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.977 ; 1.977 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.977 ; 1.977 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.362 ; 2.362 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.680 ; 2.680 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.031 ; 3.031 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.090 ; 3.090 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.054 ; 3.054 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.984 ; 1.984 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.646 ; 1.646 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.290 ; 1.290 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.290 ; 1.290 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.280 ; 1.280 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.612 ; 1.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.602 ; 1.602 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.612 ; 1.612 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.514 ; 3.153 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.605 ; 5.244 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.605 ; 5.244 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.217     ; 2.288     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.865     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.865     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.865     ; 2.936     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.231     ; 3.302     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.555     ; 3.626     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.868     ; 3.939     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.927     ; 3.998     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.914     ; 3.985     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.877     ; 2.948     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.560     ; 2.631     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.227     ; 2.298     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.227     ; 2.298     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.217     ; 2.288     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.503     ; 2.574     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.493     ; 2.564     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.503     ; 2.574     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.885     ; 4.261     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 5.464     ; 5.840     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 5.464     ; 5.840     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.272     ; 1.408     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.893     ; 2.029     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.893     ; 2.029     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.893     ; 2.029     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.245     ; 2.381     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.556     ; 2.692     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.856     ; 2.992     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.913     ; 3.049     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.901     ; 3.037     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.906     ; 2.042     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.602     ; 1.738     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.282     ; 1.418     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.282     ; 1.418     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.272     ; 1.408     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.546     ; 1.682     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.536     ; 1.672     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.546     ; 1.682     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.021     ; 3.382     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 4.849     ; 5.210     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 4.849     ; 5.210     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                           ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -1.924 ; -75.818       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.584 ; -18.506       ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -0.191 ; -0.191        ;
; FPGA_CLK                                                                            ; 0.301  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 3.494  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 7.025  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                            ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.684 ; -26.206       ;
; FPGA_CLK                                                                            ; -0.586 ; -0.586        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.151  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.154  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 11.450 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                        ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.139 ; -10.243       ;
; FPGA_CLK                                                                            ; 0.294  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.635  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 9.754  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 15.227 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                         ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; FPGA_CLK                                                                            ; -0.474 ; -12.199       ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -0.056 ; -0.496        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 1.043  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.227  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1.465  ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+--------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                             ;
+-------------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                               ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.655  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 5.801  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.561  ; 0.000         ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9.381  ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.369 ; 0.000         ;
; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.601 ; 0.000         ;
; FPGA_CLK                                                                            ; 89.498 ; 0.000         ;
+-------------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                          ; To Node                                                                                                                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -1.924 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[7]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[7]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.265     ; 0.617      ;
; -1.899 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[8]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[8]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.265     ; 0.592      ;
; -1.865 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[6]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[6]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.086     ; 0.737      ;
; -1.783 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[1] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.270     ; 0.471      ;
; -1.776 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.270     ; 0.464      ;
; -1.773 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeIntInSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.270     ; 0.461      ;
; -1.771 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|SIEReceiver:u_SIEReceiver|connectState[0] ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connectStateInSTB_reg1[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.270     ; 0.459      ;
; -1.766 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[4]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[4]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.461      ;
; -1.745 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[10]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[10]    ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.613      ;
; -1.741 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[1]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[1]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.609      ;
; -1.724 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[2]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.592      ;
; -1.701 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[9]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[9]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.396      ;
; -1.692 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[3]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[3]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.387      ;
; -1.692 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[0]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[0]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.387      ;
; -1.690 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacket:u_sendPacket|frameNum[5]                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[5]     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.385      ;
; -1.683 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[1]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[1]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.269     ; 0.372      ;
; -1.681 ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|synchronizer:tick_toggle_synchronizer|ff_reg[2]                                                                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.263     ; 0.376      ;
; -1.617 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[11]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[11]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.494      ;
; -1.596 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.460      ;
; -1.595 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.459      ;
; -1.594 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[3]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.461      ;
; -1.592 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.459      ;
; -1.581 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.448      ;
; -1.532 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.396      ;
; -1.532 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.396      ;
; -1.531 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.395      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.386      ;
; -1.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.094     ; 0.386      ;
; -1.520 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXOverflow                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[2]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.387      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|stallRxed                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[5]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[1]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.384      ;
; -1.518 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|NAKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[4]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.385      ;
; -1.517 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[0]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.383      ;
; -1.516 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.090     ; 0.384      ;
; -1.510 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqExtend[0]      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|clrTransReqSTB[2]         ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.095     ; 0.373      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[14]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[14]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.386      ;
; -1.509 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[8]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[8]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.386      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[15]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[15]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.385      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[9]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[9]       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.385      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|ACKRxed                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[6]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.091     ; 0.375      ;
; -1.508 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[12]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[12]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.385      ;
; -1.507 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[13]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[13]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.384      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[10]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFTimerSTB_reg1[10]      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.081     ; 0.383      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[7]  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.372      ;
; -1.506 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInExtend[0]        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInSTB[2]           ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.092     ; 0.372      ;
; -1.504 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                          ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.374      ;
; -1.502 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reset_n_reg                                                                                                                                             ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[2]                                                                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.121        ; -1.088     ; 0.372      ;
; 7.208  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.363      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.275  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp1_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 4.296      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.459  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp3_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.067     ; 4.119      ;
; 7.511  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.069     ; 4.065      ;
; 7.514  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.071     ; 4.060      ;
; 7.526  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.068     ; 4.051      ;
; 7.526  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.068     ; 4.051      ;
; 7.599  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.980      ;
; 7.599  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.980      ;
; 7.599  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.980      ;
; 7.599  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.980      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[5]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[0]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[2]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[4]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.624  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.066     ; 3.955      ;
; 7.667  ; ram_do_reg[4]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.087     ; 3.891      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.675  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.074     ; 3.896      ;
; 7.682  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.073     ; 3.890      ;
; 7.682  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.073     ; 3.890      ;
; 7.682  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.073     ; 3.890      ;
; 7.727  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[1]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.836      ;
; 7.727  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[3]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 3.836      ;
; 7.734  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 3.836      ;
; 7.734  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 3.836      ;
; 7.734  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.075     ; 3.836      ;
; 7.742  ; ram_do_reg[2]                                                                                                                                                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.090     ; 3.813      ;
; 7.744  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[6]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.071     ; 3.830      ;
; 7.744  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[1]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.071     ; 3.830      ;
; 7.744  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[3]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.071     ; 3.830      ;
; 7.744  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp2_reg[7]                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.071     ; 3.830      ;
; 7.762  ; sdram_request_complete_reg                                                                                                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Y[2]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.081     ; 3.802      ;
+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                                                                           ; To Node                                                                                                                                                                                           ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.103      ;
; -0.531 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.050      ;
; -0.525 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.044      ;
; -0.522 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.041      ;
; -0.513 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.032      ;
; -0.507 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.026      ;
; -0.504 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.023      ;
; -0.500 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                                                                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 1.012      ;
; -0.499 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 1.011      ;
; -0.497 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.628      ; 1.011      ;
; -0.482 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 1.001      ;
; -0.466 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.979      ;
; -0.460 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.973      ;
; -0.454 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.973      ;
; -0.452 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.971      ;
; -0.451 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.969      ;
; -0.448 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.961      ;
; -0.445 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.964      ;
; -0.440 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.959      ;
; -0.439 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.957      ;
; -0.436 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.955      ;
; -0.434 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.953      ;
; -0.433 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.952      ;
; -0.432 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.951      ;
; -0.430 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.942      ;
; -0.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.947      ;
; -0.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                                                                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.947      ;
; -0.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.940      ;
; -0.427 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.946      ;
; -0.422 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.935      ;
; -0.421 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.934      ;
; -0.418 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                                                                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.937      ;
; -0.416 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.935      ;
; -0.411 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.930      ;
; -0.409 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.927      ;
; -0.409 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.927      ;
; -0.405 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                                                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1          ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.632      ; 0.923      ;
; -0.405 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.627      ; 0.918      ;
; -0.403 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                                                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.626      ; 0.915      ;
; -0.402 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                                                                            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.921      ;
; -0.390 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.633      ; 0.909      ;
; 8.378  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.343     ; 2.881      ;
; 8.433  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.345     ; 2.824      ;
; 8.759  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|idle_state          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.925      ; 3.570      ;
; 8.830  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|idle_state                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.924      ; 3.498      ;
; 8.871  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.924      ; 3.457      ;
; 8.898  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.924      ; 3.430      ;
; 8.920  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.520      ;
; 8.946  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_wait_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.925      ; 3.383      ;
; 8.958  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.925      ; 3.371      ;
; 8.962  ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                                                                                                                                                                                                 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|areset_init_state_1 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.417       ; 1.924      ; 3.366      ;
; 9.087  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.353      ;
; 9.099  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C0_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.339      ;
; 9.106  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C2_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.332      ;
; 9.124  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[3]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.313      ;
; 9.199  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[4]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.238      ;
; 9.201  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C1_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.237      ;
; 9.257  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C3_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.181      ;
; 9.259  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.181      ;
; 9.284  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.153      ;
; 9.288  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_post_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.163     ; 2.151      ;
; 9.289  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[2]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 2.148      ;
; 9.325  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.113      ;
; 9.334  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.104      ;
; 9.341  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[1]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.099      ;
; 9.414  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 2.026      ;
; 9.422  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|reconfig_to_pal_reg                                                                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.161     ; 2.019      ;
; 9.429  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 2.009      ;
; 9.440  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|reconfig_seq_data_state                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.163     ; 1.999      ;
; 9.442  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|lpm_counter:cntr14|cntr_heo:auto_generated|counter_reg_bit[0]                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.165     ; 1.995      ;
; 9.480  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 1.958      ;
; 9.483  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|C4_data_state                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.164     ; 1.955      ;
; 9.486  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                                               ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 1.954      ;
; 9.605  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.162     ; 1.835      ;
; 9.742  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C4_data_state                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.163     ; 1.697      ;
; 9.871  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate2_state                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.013     ; 0.519      ;
; 9.951  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate2_state                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 10.416       ; -0.013     ; 0.439      ;
; 16.115 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 4.668      ;
; 16.118 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 4.665      ;
; 16.131 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|HCTxPortArbiter:u_HCTxPortArbiter|CurrState_HCTxArb.000                                                                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.037     ; 4.652      ;
; 16.266 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.510      ;
; 16.269 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.507      ;
; 16.278 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.498      ;
; 16.281 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.495      ;
; 16.282 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[0]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.494      ;
; 16.294 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[3]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.482      ;
; 16.320 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.456      ;
; 16.323 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.453      ;
; 16.336 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[4]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.440      ;
; 16.379 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.397      ;
; 16.382 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.394      ;
; 16.394 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.382      ;
; 16.395 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[2]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.381      ;
; 16.397 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.379      ;
; 16.410 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[6]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.366      ;
; 16.428 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.348      ;
; 16.431 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|sendPacketArbiterReq               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.345      ;
; 16.444 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[1]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.332      ;
; 16.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.020     ; 5.549      ;
; 16.567 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFController:u_SOFController|SOFTimer[5]                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 20.833       ; -0.044     ; 4.209      ;
+--------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; -0.191 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 1.467        ; -0.915     ; 0.581      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: 'FPGA_CLK'                                                                                                                                                                                                                                                                                               ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack   ; From Node                                                                             ; To Node                                                                               ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.301   ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.792      ; 2.244      ;
; 96.513  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; -0.778     ; 2.696      ;
; 98.645  ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8           ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout ; FPGA_CLK                                                                            ; FPGA_CLK    ; 100.000      ; 0.683      ; 0.907      ;
; 198.371 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.581      ;
; 198.375 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.577      ;
; 198.439 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.513      ;
; 198.440 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.512      ;
; 198.443 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.509      ;
; 198.444 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.508      ;
; 198.454 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.498      ;
; 198.491 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.461      ;
; 198.507 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.445      ;
; 198.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.444      ;
; 198.508 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.444      ;
; 198.511 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.441      ;
; 198.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.440      ;
; 198.512 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.440      ;
; 198.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.430      ;
; 198.522 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.430      ;
; 198.558 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.394      ;
; 198.559 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.393      ;
; 198.574 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.378      ;
; 198.575 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.377      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.376      ;
; 198.576 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.376      ;
; 198.578 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.374      ;
; 198.579 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.373      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.372      ;
; 198.580 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.372      ;
; 198.583 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.369      ;
; 198.590 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.362      ;
; 198.590 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.362      ;
; 198.620 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.332      ;
; 198.626 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.326      ;
; 198.627 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.325      ;
; 198.642 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.310      ;
; 198.643 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.309      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.308      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.308      ;
; 198.644 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.308      ;
; 198.646 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.306      ;
; 198.647 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.305      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.304      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.304      ;
; 198.648 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.304      ;
; 198.651 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.301      ;
; 198.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.294      ;
; 198.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.294      ;
; 198.658 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.294      ;
; 198.688 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.264      ;
; 198.694 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.258      ;
; 198.695 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.257      ;
; 198.696 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.256      ;
; 198.710 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.242      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.241      ;
; 198.711 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.241      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.240      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.240      ;
; 198.712 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.240      ;
; 198.714 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.238      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.237      ;
; 198.715 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.237      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.236      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.236      ;
; 198.716 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.236      ;
; 198.719 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.233      ;
; 198.726 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.226      ;
; 198.726 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.226      ;
; 198.726 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.226      ;
; 198.727 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.225      ;
; 198.756 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.196      ;
; 198.762 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.190      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.189      ;
; 198.763 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.189      ;
; 198.764 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.188      ;
; 198.778 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.174      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.173      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.172      ;
; 198.779 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.173      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.172      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.172      ;
; 198.780 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.172      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.169      ;
; 198.782 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.170      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.036     ; 1.168      ;
; 198.783 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.169      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.168      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.168      ;
; 198.784 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.168      ;
; 198.787 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.165      ;
; 198.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.158      ;
; 198.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.158      ;
; 198.794 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.158      ;
; 198.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.157      ;
; 198.795 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.157      ;
; 198.824 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.128      ;
; 198.830 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.122      ;
; 198.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                           ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.121      ;
; 198.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.121      ;
; 198.831 ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                            ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                           ; FPGA_CLK                                                                            ; FPGA_CLK    ; 200.000      ; -0.035     ; 1.121      ;
+---------+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 3.494 ; SDRAM_ADDR[21]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.105      ;
; 3.518 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.081      ;
; 3.535 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.058      ;
; 3.560 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 2.039      ;
; 3.570 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.022      ;
; 3.570 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 2.022      ;
; 3.576 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.017      ;
; 3.577 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[9]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 2.016      ;
; 3.612 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.980      ;
; 3.612 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.980      ;
; 3.613 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.981      ;
; 3.618 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.975      ;
; 3.655 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.939      ;
; 3.720 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.880      ;
; 3.721 ; SDRAM_ADDR[22]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10]                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.881      ;
; 3.746 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.847      ;
; 3.762 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.838      ;
; 3.769 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.829      ;
; 3.769 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.829      ;
; 3.769 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.829      ;
; 3.769 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.829      ;
; 3.788 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.805      ;
; 3.811 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.787      ;
; 3.811 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.787      ;
; 3.811 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.787      ;
; 3.811 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.787      ;
; 3.855 ; SDRAM_ADDR[16]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.745      ;
; 3.865 ; SDRAM_ADDR[7]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.125     ; 1.733      ;
; 3.892 ; SDRAM_ADDR[9]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.130     ; 1.701      ;
; 3.903 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.696      ;
; 3.923 ; SDRAM_ADDR[8]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.131     ; 1.669      ;
; 3.927 ; SDRAM_ADDR[15]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.679      ;
; 3.945 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.654      ;
; 3.947 ; SDRAM_ADDR[19]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.653      ;
; 3.956 ; SDRAM_ADDR[5]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.129     ; 1.638      ;
; 3.996 ; SDRAM_ADDR[6]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.603      ;
; 4.003 ; SDRAM_ADDR[3]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.601      ;
; 4.053 ; SDRAM_ADDR[18]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.122     ; 1.548      ;
; 4.069 ; SDRAM_ADDR[14]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.537      ;
; 4.104 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.549      ;
; 4.106 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.547      ;
; 4.107 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.546      ;
; 4.108 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.545      ;
; 4.109 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.544      ;
; 4.109 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.544      ;
; 4.109 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.544      ;
; 4.110 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.117     ; 1.543      ;
; 4.119 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.481      ;
; 4.161 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_ras_n                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.439      ;
; 4.162 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[0]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.484      ;
; 4.166 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.480      ;
; 4.166 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[10]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.480      ;
; 4.167 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.479      ;
; 4.167 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.479      ;
; 4.168 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[8]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.478      ;
; 4.168 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[9]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.478      ;
; 4.169 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[1]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.477      ;
; 4.182 ; SDRAM_ADDR[20]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.420      ;
; 4.202 ; SDRAM_ADDR[4]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.400      ;
; 4.207 ; SDRAM_ADDR[2]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.395      ;
; 4.214 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:0:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.915     ; 0.582      ;
; 4.218 ; SDRAM_ADDR[17]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.381      ;
; 4.222 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.434      ;
; 4.254 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.402      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[25]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[26]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[27]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[23]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[31]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.280 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[30]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.124     ; 1.366      ;
; 4.284 ; SDRAM_ADDR[1]                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.318      ;
; 4.286 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.370      ;
; 4.287 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.369      ;
; 4.295 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[29]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.352      ;
; 4.295 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[28]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.352      ;
; 4.295 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[24]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.352      ;
; 4.295 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[20]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.123     ; 1.352      ;
; 4.311 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.111     ; 1.348      ;
; 4.314 ; SDRAM_ADDR[0]                                                                             ; ram_bena_reg[0]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.114     ; 1.342      ;
; 4.315 ; SDRAM_ADDR[10]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.126     ; 1.282      ;
; 4.329 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_bena_reg[1]                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.111     ; 1.330      ;
; 4.331 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.318      ;
; 4.344 ; SDRAM_ADDR[13]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.258      ;
; 4.345 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.304      ;
; 4.352 ; SDRAM_ADDR[12]                                                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[0]                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.250      ;
; 4.352 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[6]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.297      ;
; 4.353 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[11]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.296      ;
; 4.354 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[14]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.295      ;
; 4.434 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[13]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.223      ;
; 4.437 ; SDRAM_WIDTH_8BIT_ACCESS                                                                   ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.113     ; 1.220      ;
; 4.443 ; SDRAM_WRITE_ENABLE                                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.208      ;
; 4.469 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[2]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.182      ;
; 4.469 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.182      ;
; 4.473 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[4]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.176      ;
; 4.473 ; SDRAM_READ_ENABLE                                                                         ; ram_do_reg[12]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.121     ; 1.176      ;
; 4.485 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[5]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.165      ;
; 4.485 ; SDRAM_READ_ENABLE                                                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.119     ; 1.166      ;
; 4.486 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[3]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.164      ;
; 4.486 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[15]                                                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.164      ;
; 4.486 ; SDRAM_WRITE_ENABLE                                                                        ; ram_di_reg[7]                                                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.873        ; -0.120     ; 1.164      ;
+-------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                              ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 7.025  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0]                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:4:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 8.810        ; -0.915     ; 0.708      ;
; 13.014 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.129     ; 4.328      ;
; 13.097 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 4.264      ;
; 13.182 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 4.181      ;
; 13.212 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 4.151      ;
; 13.226 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 4.137      ;
; 13.253 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 4.135      ;
; 13.280 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 4.081      ;
; 13.281 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.128     ; 4.062      ;
; 13.309 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.109     ; 4.053      ;
; 13.366 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[2]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 3.999      ;
; 13.368 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 3.995      ;
; 13.375 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.130     ; 3.966      ;
; 13.375 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 3.988      ;
; 13.399 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.109     ; 3.963      ;
; 13.443 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 3.945      ;
; 13.452 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 3.936      ;
; 13.564 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.109     ; 3.798      ;
; 13.613 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 3.775      ;
; 13.640 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 3.748      ;
; 13.677 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.710      ;
; 13.682 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.725      ;
; 13.692 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.715      ;
; 13.718 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.689      ;
; 13.764 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.645      ;
; 13.775 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.634      ;
; 13.782 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.605      ;
; 13.784 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.603      ;
; 13.794 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.613      ;
; 13.809 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.600      ;
; 13.853 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.556      ;
; 13.862 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 3.527      ;
; 13.879 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.529      ;
; 13.891 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.517      ;
; 13.895 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.514      ;
; 13.896 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.128     ; 3.447      ;
; 13.899 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.488      ;
; 13.912 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.496      ;
; 13.935 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.474      ;
; 13.949 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 3.440      ;
; 13.950 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.459      ;
; 13.969 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.438      ;
; 13.989 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.420      ;
; 14.011 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.396      ;
; 14.018 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.391      ;
; 14.019 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.390      ;
; 14.020 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.367      ;
; 14.030 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.379      ;
; 14.043 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.084     ; 3.344      ;
; 14.043 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.366      ;
; 14.045 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.364      ;
; 14.073 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.336      ;
; 14.090 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.318      ;
; 14.096 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.311      ;
; 14.105 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 3.284      ;
; 14.112 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 3.277      ;
; 14.113 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 3.276      ;
; 14.113 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.294      ;
; 14.140 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.269      ;
; 14.146 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.263      ;
; 14.149 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.258      ;
; 14.150 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.258      ;
; 14.153 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.256      ;
; 14.159 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.250      ;
; 14.161 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.246      ;
; 14.217 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.063     ; 3.191      ;
; 14.236 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.173      ;
; 14.262 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.147      ;
; 14.270 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.139      ;
; 14.273 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.136      ;
; 14.281 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.128      ;
; 14.292 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 3.115      ;
; 14.301 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.108      ;
; 14.338 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.071      ;
; 14.341 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 3.068      ;
; 14.366 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.106     ; 2.999      ;
; 14.401 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.083     ; 2.987      ;
; 14.416 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.973      ;
; 14.425 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.964      ;
; 14.515 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.874      ;
; 14.525 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.864      ;
; 14.547 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 2.862      ;
; 14.550 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.754      ;
; 14.577 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.812      ;
; 14.577 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.812      ;
; 14.610 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[6]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.105     ; 2.756      ;
; 14.612 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.777      ;
; 14.625 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 2.784      ;
; 14.643 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hsync_reg                                                           ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.115     ; 2.713      ;
; 14.651 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.738      ;
; 14.664 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 2.743      ;
; 14.722 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.216     ; 2.580      ;
; 14.726 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.062     ; 2.683      ;
; 14.744 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.082     ; 2.645      ;
; 14.754 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.218     ; 2.546      ;
; 14.764 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.057     ; 2.650      ;
; 14.767 ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.214     ; 2.537      ;
; 14.779 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 2.628      ;
; 14.803 ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                                  ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.064     ; 2.604      ;
; 14.828 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[2]                                                                                                    ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.088     ; 2.602      ;
+--------+--------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                  ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                                                                                                                                        ; To Node                                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.684 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[4]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedRate_reg1                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.777      ;
; -0.681 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[1]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[1]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.780      ;
; -0.679 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.783      ;
; -0.678 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[1]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[1]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.777      ;
; -0.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSyncSTB                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSync_reg1                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.790      ;
; -0.671 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEnSTB                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|preambleEn_reg1                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.790      ;
; -0.670 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[5]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.784      ;
; -0.668 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.794      ;
; -0.668 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[2]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|LineDirectControlEn_reg1                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.793      ;
; -0.666 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[1]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[1]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.789      ;
; -0.665 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|RxfifoBI:u_RxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.796      ;
; -0.665 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[6]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.789      ;
; -0.664 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[3]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|fullSpeedPol_reg1                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.797      ;
; -0.661 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.801      ;
; -0.659 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[2]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[2]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.802      ;
; -0.655 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[1]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[1]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.806      ;
; -0.653 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeRegSTB[0]                    ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg_reg1[0]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.802      ;
; -0.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggle                                                      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|TxfifoBI:u_TxfifoBI|forceEmptyToggleSyncToUsbClk[0]                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.809      ;
; -0.652 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.802      ;
; -0.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPRegSTB[3]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxEndPReg_reg1[3]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.815      ;
; -0.647 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineControlReg[0]                     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxLineState_reg1[0]                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.814      ;
; -0.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEnSTB                                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|isoEn_reg1                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.817      ;
; -0.644 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[2]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.810      ;
; -0.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableReg_reg1                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.819      ;
; -0.643 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[3]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[3]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.818      ;
; -0.642 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[0]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[0]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.819      ;
; -0.636 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[5]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[5]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.825      ;
; -0.632 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[4]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.822      ;
; -0.628 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrRegSTB[0]                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.262      ; 0.826      ;
; -0.622 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[6]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[6]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.839      ;
; -0.614 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.841      ;
; -0.610 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstShift[0]                                                                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.263      ; 0.845      ;
; -0.604 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[2]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[2]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.858      ;
; -0.600 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[3]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[3]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.862      ;
; -0.595 ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[4]                                                                                                                                                              ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pal_synchronizer|ff_reg[2]                                                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.264      ; 0.861      ;
; -0.592 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndex[4]                                                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferOutIndexSyncToWrClk[4]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.269      ; 0.869      ;
; -0.592 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[4]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[4]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.870      ;
; -0.587 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[6]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[6]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.875      ;
; -0.584 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[0]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[0]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.878      ;
; -0.577 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[1]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.885      ;
; -0.561 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndex[5]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|bufferInIndexSyncToRdClk[5]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.270      ; 0.901      ;
; 0.176  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|bufferInIndex[1]                                                           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.219      ; 0.499      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.010                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.100                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1101                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.011                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.001                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RXByteStMachCurrState.101                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CurrState_prRxByte.1110                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processTxByte:u_processTxByte|TXOneCount[1]                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C3_data_state                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C2_data_state                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C1_data_state                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|C0_data_state                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                            ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_seq_data_state                                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_post_state                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|reconfig_wait_state                                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                      ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_state_reg[0]                                                                                                                                                                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                        ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pll_enable_reg                                                                                                                                                                                        ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|SOFTxGnt                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.110                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.001                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.010                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.011                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|SOFTimerClr                                                                       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.100                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|CurrState_SOFTx.101                                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[0]                                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[1]                                                                              ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|sendPacketArbiter:u_sendPacketArbiter|CurrState_sendPktArb.01                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[0]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[2]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[3]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitCount[1]                                               ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1101                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1110                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.10                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.11                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy             ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxBitRdy                                             ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[1]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxBits[0]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100      ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1100                                      ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01     ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.01                                     ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXByte[7]                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn            ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|processRxByteWEn                                            ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[3]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[2]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[6]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[7]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[0]                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[0]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RxCtrlOut[1]                                                ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxCtrl[1]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|RxByte[5]                                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                   ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxByte:u_processRxByte|CRC16En                                                   ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[1]                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[2]                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:RxUpdateCRC16|i[3]                                                          ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
+--------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: 'FPGA_CLK'                                                                                                                                                                                                                                                                                   ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                       ; To Node                                                                         ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.586 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[131]                                 ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.227      ; 1.891      ;
; 0.192  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.312      ;
; 0.205  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.325      ;
; 0.264  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2] ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1] ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.384      ;
; 0.297  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.417      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.298  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.418      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.299  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.419      ;
; 0.300  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.420      ;
; 0.305  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.425      ;
; 0.306  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.426      ;
; 0.306  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.426      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.427      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.427      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.427      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.427      ;
; 0.307  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.427      ;
; 0.308  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.428      ;
; 0.311  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.431      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.411  ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.531      ;
; 0.446  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.566      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.567      ;
; 0.447  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.567      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.568      ;
; 0.448  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.568      ;
; 0.454  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.574      ;
; 0.455  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.576      ;
; 0.455  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.575      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.456  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.576      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.457  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.577      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.578      ;
; 0.458  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.579      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.579      ;
; 0.459  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.579      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.460  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.580      ;
; 0.461  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.581      ;
; 0.464  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.584      ;
; 0.465  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.585      ;
; 0.465  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.585      ;
; 0.465  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.585      ;
; 0.466  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.586      ;
; 0.467  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.587      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.468  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.588      ;
; 0.469  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.589      ;
; 0.509  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.630      ;
; 0.509  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.629      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.630      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.630      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.630      ;
; 0.510  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.630      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.631      ;
; 0.511  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.631      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.633      ;
; 0.512  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.632      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.633      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.633      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.633      ;
; 0.513  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.633      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.634      ;
; 0.514  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.634      ;
; 0.517  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.637      ;
; 0.518  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.638      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.639      ;
; 0.519  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.639      ;
; 0.520  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.640      ;
; 0.521  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.036      ; 0.641      ;
; 0.521  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                      ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.642      ;
; 0.521  ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                     ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                     ; FPGA_CLK                                                                            ; FPGA_CLK    ; 0.000        ; 0.037      ; 0.642      ;
+--------+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                                                                                     ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.279      ; 0.644      ;
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                        ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                              ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                            ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                                                                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.307      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.193 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.313      ;
; 0.194 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; half_scandouble_enable_reg                                                                       ; half_scandouble_enable_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.315      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.195 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.314      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.315      ;
; 0.196 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.317      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.197 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.316      ;
; 0.198 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.317      ;
; 0.198 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.317      ;
; 0.205 ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                    ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.325      ;
; 0.207 ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                                             ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.327      ;
; 0.227 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.718      ;
; 0.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.271      ; 0.713      ;
; 0.238 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[3] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.729      ;
; 0.243 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.279      ; 0.736      ;
; 0.244 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.277      ; 0.735      ;
; 0.252 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.279      ; 0.745      ;
; 0.260 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.037      ; 0.381      ;
; 0.261 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.381      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.262 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.382      ;
; 0.263 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.383      ;
; 0.264 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.384      ;
; 0.265 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.384      ;
; 0.265 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.384      ;
; 0.265 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.035      ; 0.384      ;
; 0.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6] ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.279      ; 0.759      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.266 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]                      ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.386      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                    ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
; 0.267 ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                     ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.036      ; 0.387      ;
+-------+--------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                                                                   ; To Node                                                                                                                                                                                                                          ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.154 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[6]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.476      ;
; 0.161 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[2]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.483      ;
; 0.163 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.485      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[7]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.495      ;
; 0.173 ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                                                                                         ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.221      ; 0.498      ;
; 0.174 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[5]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.498      ;
; 0.177 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[4]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.501      ;
; 0.179 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.307      ;
; 0.179 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[3]   ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.218      ; 0.501      ;
; 0.180 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[0]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.504      ;
; 0.181 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|cntr_o8b:wr_ptr|counter_reg_bit[0] ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.219      ; 0.504      ;
; 0.182 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[2]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.506      ;
; 0.184 ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_command_count_reg[3]                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.220      ; 0.508      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[2]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[2]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.185 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB_reg1[0]                 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPIDInSTB[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.313      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                                                                             ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_popped                                                                                                                                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c1_write_reg                                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[1]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[2]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|count_reg[3]                                                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[1]                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                                                                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|scl_ena                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|bit_cnt[1]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[2]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|state.command                                                                                                                                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[7]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                      ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master1|scl_ena                                                                                                                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                   ; zpucore:zpu|zpu_config_regs:config_regs|i2c_master:i2c_master0|data_rx[4]                                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB_reg1[2]              ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|frameNumInSTB[2]                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                  ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxSOFEnableRegSTB                                       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                                                                                                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                                                                                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[1]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[2]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[3]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[4]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[5]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[6]                                                                                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                        ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReqSTB                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|connEventInt                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                          ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|resumeInt                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                         ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|SOFSentInt                                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB_reg1[3]           ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|RxPktStatusInSTB[3]                                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                               ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|hostMode                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transDoneInt                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[2]                                                                                                                   ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[1]                                                                                                                                        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.044      ; 0.314      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                                                                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|first_line_of_instruction_reg                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                                                                                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[7]                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf2_reg[3]                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                                                                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[1]                                                                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|allpot_reg[1]                                                                                                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[4]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[0]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[1]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[2]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[3]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[6]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[5]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf0_reg[7]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0]                                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[1]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[3]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[2]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[4]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
; 0.186 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[7]                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:\gen_stereo:pokey2|audf1_reg[7]                                                                                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.037      ; 0.307      ;
+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_init_fsm[1]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_reg                                                                                      ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_complete_reg                                                                             ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                               ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.202 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.322      ;
; 0.205 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.325      ;
; 0.207 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.327      ;
; 0.216 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.336      ;
; 0.226 ; seq_reg[10]                                                                                            ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.346      ;
; 0.253 ; ram_bena_reg[0]                                                                                        ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.373      ;
; 0.254 ; ram_bena_reg[1]                                                                                        ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.374      ;
; 0.280 ; seq_reg[9]                                                                                             ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.400      ;
; 0.283 ; seq_reg[8]                                                                                             ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.403      ;
; 0.287 ; seq_reg[2]                                                                                             ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.407      ;
; 0.290 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.410      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                              ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.320 ; sdram_ctrl:sdram_controller|r_rd_reg                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.440      ;
; 0.323 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                              ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.443      ;
; 0.342 ; sdram_ctrl:sdram_controller|r_refr_act                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.462      ;
; 0.361 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.481      ;
; 0.373 ; seq_reg[3]                                                                                             ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.493      ;
; 0.397 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.516      ;
; 0.401 ; sdram_ctrl:sdram_controller|r_rd_act                                                                   ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.521      ;
; 0.411 ; sdram_request_reg                                                                                      ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.531      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.444 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.564      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.458 ; seq_reg[1]                                                                                             ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.578      ;
; 0.461 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.580      ;
; 0.471 ; seq_reg[4]                                                                                             ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.588      ;
; 0.473 ; seq_reg[4]                                                                                             ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.591      ;
; 0.477 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 0.751      ;
; 0.485 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.605      ;
; 0.500 ; seq_reg[7]                                                                                             ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.620      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
; 0.507 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.627      ;
; 0.508 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.628      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.629      ;
; 0.510 ; seq_reg[11]                                                                                            ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.510 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.630      ;
; 0.514 ; seq_reg[0]                                                                                             ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.634      ;
; 0.516 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.637      ;
; 0.518 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.638      ;
; 0.519 ; seq_reg[1]                                                                                             ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.519 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.639      ;
; 0.521 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.641      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.522 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.642      ;
; 0.524 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                               ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.033      ; 0.641      ;
; 0.526 ; sdram_ctrl:sdram_controller|r_refr_req                                                                 ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.037      ; 0.647      ;
; 0.532 ; seq_reg[9]                                                                                             ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.652      ;
; 0.536 ; seq_reg[11]                                                                                            ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.656      ;
; 0.546 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.666      ;
; 0.555 ; seq_reg[0]                                                                                             ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.675      ;
; 0.558 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.004      ; 0.620      ;
; 0.558 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.004      ; 0.620      ;
; 0.558 ; sdram_ctrl:sdram_controller|r_wr_act                                                                   ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.004      ; 0.620      ;
; 0.562 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.684      ;
; 0.563 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.685      ;
; 0.565 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                  ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.038      ; 0.687      ;
; 0.571 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.691      ;
; 0.572 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                              ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.692      ;
+-------+--------------------------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                                                                                                                                                                                              ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                                 ; To Node                                                                                                                                             ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 11.450 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:pll_enable_synchronizer|ff_reg[0] ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -10.281      ; -0.781     ; 0.525      ;
+--------+-------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                           ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.139 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.639      ; 1.664      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.138 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.059        ; 0.636      ; 1.660      ;
; -1.025 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.638      ; 1.614      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
; -1.024 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.124        ; 0.635      ; 1.610      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: 'FPGA_CLK'                                                                                                                                                                                                                                                                               ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.784      ; 2.243      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.294 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.785      ; 2.244      ;
; 0.303 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.886        ; 1.777      ; 2.227      ;
+-------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                            ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.133     ; 1.829      ;
; 9.635 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.139     ; 1.823      ;
; 9.637 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.187     ; 1.771      ;
; 9.637 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.193     ; 1.765      ;
; 9.637 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.826      ;
; 9.637 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.826      ;
; 9.637 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.826      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.768      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.768      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.768      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.135     ; 1.823      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.135     ; 1.823      ;
; 9.639 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.135     ; 1.823      ;
; 9.640 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.128     ; 1.829      ;
; 9.641 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 1.765      ;
; 9.641 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 1.765      ;
; 9.641 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.189     ; 1.765      ;
; 9.642 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 1.771      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.137     ; 1.816      ;
; 9.644 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.134     ; 1.819      ;
; 9.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.108     ; 1.844      ;
; 9.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.842      ;
; 9.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.110     ; 1.842      ;
; 9.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.843      ;
; 9.645 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.843      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.191     ; 1.758      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.188     ; 1.761      ;
; 9.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.109     ; 1.842      ;
; 9.647 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.129     ; 1.821      ;
; 9.647 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.128     ; 1.822      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.182     ; 1.764      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.183     ; 1.763      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.823      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.823      ;
; 9.649 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.125     ; 1.823      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.765      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.765      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.179     ; 1.765      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.894      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.894      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.894      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.894      ;
; 9.651 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.894      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.835      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.835      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.835      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.104     ; 1.835      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.837      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.836      ;
; 9.658 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.836      ;
; 9.664 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.101     ; 1.879      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.666 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.103     ; 1.875      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.862      ;
; 9.682 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.862      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.720      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.720      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.720      ;
; 9.775 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.102     ; 1.720      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.672      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.672      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.672      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.100     ; 1.670      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.673      ;
; 9.874 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.097     ; 1.672      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.670      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.099     ; 1.670      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.671      ;
; 9.875 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.747       ; -0.098     ; 1.671      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                    ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                            ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[2]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[7]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[5]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[6]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[3]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.754 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|data_out_reg[4]               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.808      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.616      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.616      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.946 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.086     ; 1.613      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[6]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|transmit_divisor_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[7]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[6]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[5]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[4]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_shift_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|p2s_transmit_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.614      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_clk_out_reg               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|sio_data_out_reg              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[2]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[3]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.947 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|s2p_state_reg[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.615      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[5]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[5]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[4]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[4]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[0]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[0]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[1]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[1]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[3]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[2]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[2]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[3]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[6]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|pending_divisor_reg[7]        ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.948 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|divisor_reg[7]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.608      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.608      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.088     ; 1.608      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 1.616      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.080     ; 1.616      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[2]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 1.617      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.084     ; 1.612      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 1.617      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[6]                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.079     ; 1.617      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.614      ;
; 9.949 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.613      ;
; 9.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.613      ;
; 9.950 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.082     ; 1.613      ;
; 9.951 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.611      ;
; 9.951 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.611      ;
; 9.951 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.748       ; -0.083     ; 1.611      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 15.227 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.131     ; 2.113      ;
; 15.228 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.132     ; 2.111      ;
; 15.230 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.130     ; 2.111      ;
; 15.230 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|b_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.130     ; 2.111      ;
; 15.238 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.123      ;
; 15.238 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.123      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.111     ; 2.121      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|hsync_reg                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 2.120      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.111     ; 2.121      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.122      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[6]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.122      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|g_reg[7]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.110     ; 2.122      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[4]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 2.120      ;
; 15.239 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|r_reg[5]                              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.112     ; 2.120      ;
; 15.467 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.107     ; 1.943      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.108     ; 1.942      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.469 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.101     ; 1.948      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
; 15.470 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 17.621       ; -0.099     ; 1.949      ;
+--------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'FPGA_CLK'                                                                                                                                                                                                                                                                                 ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                                     ; Launch Clock                                                                        ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+
; -0.474 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.212      ; 1.988      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.220      ; 2.001      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
; -0.469 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK    ; 0.066        ; 2.221      ; 2.002      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                            ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                            ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.056 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.274      ; 1.527      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; -0.055 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; 0.055        ; 1.270      ; 1.524      ;
; 0.115  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.275      ; 1.582      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
; 0.116  ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; -0.062       ; 1.271      ; 1.579      ;
+--------+--------------------------------------------------------------------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                            ; To Node                                               ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.043 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.291      ; 1.529      ;
; 1.043 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.291      ; 1.529      ;
; 1.043 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.291      ; 1.529      ;
; 1.046 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.279      ; 1.520      ;
; 1.208 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.292      ; 1.584      ;
; 1.208 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.292      ; 1.584      ;
; 1.208 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.292      ; 1.584      ;
; 1.211 ; switch_pal_ntsc:\gen_real_pll:pll_switcher|synchronizer:reset_synchronizer|ff_reg[0] ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.280      ; 1.575      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[1]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[2]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[3]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[4]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[5]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[6]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[7]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[8]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[9]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[10] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[11] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[12] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[13] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[14] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[15] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.513      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[12]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.513      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[9]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[23]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.513      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[8]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[3]       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[0]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.096      ; 1.516      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[24]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[10]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[16]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[17]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.091      ; 1.511      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.225 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.092      ; 1.512      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.518      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.518      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.515      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.518      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.515      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[1]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[4]   ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.097      ; 1.518      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[14]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.094      ; 1.515      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[16] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[17] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[18] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[19] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[20] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[21] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[22] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[23] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[24] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[25] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[26] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[27] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.514      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[28] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|timer_reg[29] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[29]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.514      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.098      ; 1.519      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[27]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.099      ; 1.520      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out6_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.514      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_config_regs:config_regs|out5_reg[28]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.093      ; 1.514      ;
; 1.226 ; sdram_ctrl:sdram_controller|sdram_rdy                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.001        ; 0.095      ; 1.516      ;
+-------+--------------------------------------------------------------------------------------+-------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                             ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.227 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.501      ;
; 1.227 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.501      ;
; 1.227 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.501      ;
; 1.227 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.501      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.499      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.499      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.499      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.499      ;
; 1.228 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.502      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.504      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.504      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.504      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.229 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.500      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.506      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.506      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.504      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.505      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.230 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.507      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.507      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.507      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.507      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.505      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.508      ;
; 1.231 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.507      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.558      ;
; 1.307 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.084      ; 1.558      ;
; 1.308 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.558      ;
; 1.308 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.083      ; 1.558      ;
; 1.402 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.676      ;
; 1.402 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.081      ; 1.676      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.412 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.078      ; 1.683      ;
; 1.414 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.080      ; 1.687      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.693      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.693      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.693      ;
; 1.418 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; -0.001       ; 0.082      ; 1.693      ;
+-------+------------------------+-----------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                                            ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node         ; To Node                                                                       ; Launch Clock                                                                        ; Latch Clock                                                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+
; 1.465 ; sdram_reset_n_reg ; half_scandouble_enable_reg                                                    ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[0]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[1]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[2]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[3]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[4]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[5]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[6]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[7]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[8]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[9]                  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|input_address_reg[10]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[0]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[1]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[2]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[3]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[4]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[5]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[6]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[7]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[8]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[9]                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|output_address_reg[10]                ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.088      ; 1.747      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[7]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[5]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[2]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[6]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[4]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[1]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.465 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[0]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.087      ; 1.746      ;
; 1.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                     ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.744      ;
; 1.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.744      ;
; 1.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                           ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.744      ;
; 1.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.744      ;
; 1.468 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                         ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.082      ; 1.744      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[94]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[93]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[92]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[91]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[90]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[89]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[88]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[87]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[86]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[85]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[84]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[83]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[82]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[81]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[80]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[79]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[78]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[77]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[76]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[75]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[74]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[73]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[72]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[71]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[70]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[69]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[68]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[67]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[66]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[65]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[64]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[63]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[62]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[61]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[60]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[59]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[58]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[57]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[56]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[55]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[54]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[53]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[52]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[51]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[50]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[49]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.080      ; 1.750      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[48]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.476 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[47]  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.081      ; 1.751      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.479 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.752      ;
; 1.480 ; sdram_reset_n_reg ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000        ; 0.079      ; 1.753      ;
+-------+-------------------+-------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.655 ; 5.871        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.656 ; 5.872        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.666 ; 5.821        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]'                                                                                                                                                                                   ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                              ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; 5.801 ; 5.870        ; 0.069          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.824 ; 5.877        ; 0.053          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|clkctrl:\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component|clkctrl1~ena_reg ;
; 5.870 ; 5.870        ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
; 5.877 ; 5.877        ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; Rise       ; \gen_real_pll:pll_switcher|\GEN_CLKCTRL:2:CLKCTRLX|clkctrl_altclkctrl_7ji_component|clkctrl1|inclk[0]                                               ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]'                                                                                                                                                                                            ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                       ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_address_reg0 ;
; 8.561 ; 8.791        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg       ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.562 ; 8.792        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_address_reg0 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_we_reg       ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0  ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_address_reg0 ;
; 8.563 ; 8.793        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg       ;
; 8.564 ; 8.794        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.565 ; 8.795        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:linea|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 8.565 ; 8.795        ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|buffer_select_reg                                                                                                    ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|colour_reg[3]                                                                                                        ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[0]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[10]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[11]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[127]                                                                                ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[12]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[13]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[14]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[15]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[16]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[17]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[18]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[19]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[1]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[20]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[21]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[22]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[23]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[24]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[25]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[26]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[27]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[28]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[29]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[2]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[30]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[31]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[32]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[33]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[34]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[35]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[36]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[37]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[38]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[39]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[3]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[40]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[41]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[42]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[43]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[44]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[45]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[46]                                                                                 ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[4]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[5]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[6]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[7]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[8]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[9]                                                                                  ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|hsync_in_reg                                                                                                         ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_hsync_reg                                                                                                        ;
; 8.592 ; 8.808        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|vga_odd_reg                                                                                                          ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[100]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[101]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[102]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[103]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[104]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[105]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[106]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[107]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[108]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[109]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[110]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[111]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[112]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[113]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[114]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[115]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[116]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[117]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[118]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[119]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[120]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[121]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[122]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[123]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[124]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[125]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[126]                                                                                ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[95]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[96]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[97]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[98]                                                                                 ;
; 8.593 ; 8.809        ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|delay_line:hsync_delay|shift_reg[99]                                                                                 ;
; 8.594 ; 8.824        ; 0.230          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_address_reg0 ;
; 8.594 ; 8.824        ; 0.230          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_datain_reg0  ;
; 8.594 ; 8.824        ; 0.230          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; Rise       ; scandoubler:\gen_video_vga:scandoubler1|scandouble_ram_infer:lineb|altsyncram:ram_block_rtl_0|altsyncram_2e81:auto_generated|ram_block1a2~porta_we_reg       ;
+-------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'usb_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                                                                                                                                                              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 9.381  ; 10.391       ; 1.010          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 9.431  ; 10.441       ; 1.010          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|pal_pll:generic_pll|altpll:altpll_component|pal_pll_altpll:auto_generated|pll1~OBSERVABLESCANDFF                                                                                                                         ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_address_reg0                 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_address_reg0 ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0                    ;
; 10.162 ; 10.392       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg                          ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|altsyncram:altsyncram4|altsyncram_9vl3:auto_generated|ram_block1a0~porta_datain_reg0                  ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|altsyncram:altsyncram4|altsyncram_erl3:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0                     ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0                    ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                                                ;
; 10.164 ; 10.394       ; 0.230          ; Low Pulse Width  ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                                                ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig:generic_pll1_reconfig|video_pll_reconfig_pllrcfg_ps41:video_pll_reconfig_pllrcfg_ps41_component|configupdate3_state                                                                                   ;
; 10.184 ; 10.400       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Fall       ; switch_pal_ntsc:\gen_real_pll:pll_switcher|video_pll_reconfig_pal:generic_pll1_reconfig_pal|video_pll_reconfig_pal_pllrcfg_uo41:video_pll_reconfig_pal_pllrcfg_uo41_component|configupdate3_state                                                                   ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.0111                                                         ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|CurrState_prRxBit.1010                                                         ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|RXBitStMachCurrState.00                                                        ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[0]                                                               ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[1]                                                               ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[2]                                                               ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[3]                                                               ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|processRxBit:u_processRxBit|resumeWaitCnt[4]                                                               ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[8]                                                                     ;
; 10.201 ; 10.417       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbSerialInterfaceEngine:u_usbSerialInterfaceEngine|updateCRC16:TxUpdateCRC16|CRCResult[9]                                                                     ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[0]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[1]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[2]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[3]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[4]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[5]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[6]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_count_reg[7]                                                                                                                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|tick_toggle_reg                                                                                                                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkFirst                                                                                                           ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|hostSlaveMuxBI:u_hostSlaveMuxBI|rstSyncToUsbClkOut                                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[2]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[3]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[4]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[5]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[6]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|SOFTransmit:u_SOFTransmit|i[7]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[2]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[3]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[4]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[5]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxAddrReg_reg1[6]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[0]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|TxTransTypeReg[1]                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|USBHostControlBI:u_USBHostControlBI|transReq_reg1                                                                              ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortCntl[0]                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[0]                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|directControl:u_directControl|HCTxPortData[1]                                                                                  ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CRCError                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00000                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00001                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.00010                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|CurrState_getPkt.01110                                                                                   ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[0]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[1]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[2]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[3]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[4]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[5]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[6]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOld[7]                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[0]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[1]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[2]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[3]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[4]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[5]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[6]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXByteOldest[7]                                                                                          ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RXTimeOut                                                                                                ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[0]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[2]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|RxPID[3]                                                                                                 ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|bitStuffError                                                                                            ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|getPacket:u_getPacket|dataSequence                                                                                             ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000011                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000100                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000101                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000110                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.000111                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001000                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001011                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.001101                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010000                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010010                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010011                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010101                                                                      ;
; 10.202 ; 10.418       ; 0.216          ; High Pulse Width ; usb_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|usbHostControl:u_usbHostControl|hostcontroller:u_hostController|CurrState_hstCntrl.010111                                                                      ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                               ; Clock Edge ; Target                                                                                                                                                                                                                                           ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a16~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a18~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a30~porta_address_reg0                                                                                                                                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_address_reg0                 ;
; 17.369 ; 17.599       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_we_reg                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_address_reg0       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_we_reg             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_address_reg0                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_we_reg                                             ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a10~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a11~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a12~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a14~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a15~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a19~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a21~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a26~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a27~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a28~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a34~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a35~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a38~porta_address_reg0                                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a3~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a4~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a5~porta_address_reg0                                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                       ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                      ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_address_reg0                                                                                                                  ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_we_reg                                                                                                                        ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_address_reg0 ;
; 17.370 ; 17.600       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_we_reg       ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a13~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a17~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a1~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a20~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a22~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a23~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a25~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a31~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a32~porta_address_reg0                                                                                                                                 ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a6~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a7~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a9~porta_address_reg0                                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_address_reg0                                                                                                                  ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_we_reg                                                                                                                        ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_address_reg0                   ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_we_reg                         ;
; 17.371 ; 17.601       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~porta_datain_reg0                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram|altsyncram:ram_block_rtl_0|altsyncram_jc41:auto_generated|ram_block1a0~porta_datain_reg0        ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|generic_ram_infer:reg_file1|altsyncram:ram_block_rtl_0|altsyncram_lc41:auto_generated|ram_block1a0~porta_datain_reg0                                        ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a8~porta_address_reg0                                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                  ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                 ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a2~porta_datain_reg0                                                                                                                   ;
; 17.372 ; 17.602       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|TxFifo:HostTxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~porta_datain_reg0  ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a24~porta_address_reg0                                                                                                                                 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:altsyncram_component|altsyncram_76a1:auto_generated|ram_block1a29~porta_address_reg0                                                                                                                                 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_hf41:auto_generated|ram_block1a0~porta_datain_reg0                                                                                                                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~porta_datain_reg0                    ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_receive:receive_fifo|scfifo:scfifo_component|scfifo_bi31:auto_generated|a_dpfifo_io31:dpfifo|altsyncram_cg81:FIFOram|ram_block1a0~portb_address_reg0                   ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|sio_handler:simple_uart_inst|fifo_transmit:transmit_fifo|scfifo:scfifo_component|scfifo_tg31:auto_generated|a_dpfifo_4n31:dpfifo|altsyncram_gd81:FIFOram|ram_block1a0~portb_address_reg0                 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|altsyncram:buffer_rtl_0|altsyncram_trc1:auto_generated|ram_block1a0~portb_address_reg0 ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[0]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[1]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[2]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[3]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[4]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[5]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[6]                                                                             ;
; 17.373 ; 17.603       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|usbHostCyc2Wrap_usb1t11:\USBGEN:0:usbcon|usbHost:usbHostInst|RxFifo:HostRxFifo|fifoRTL:u_fifo|dpMem_dc:u_dpMem_dc|dataOut[7]                                                                             ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[0]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[10]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[11]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[12]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[13]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[14]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[15]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[18]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[19]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[1]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[20]                                                                                                                                                                                                                                   ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[2]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[4]                                                                                                                                                                                                                                    ;
; 17.392 ; 17.608       ; 0.216          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; Fall       ; SDRAM_ADDR[5]                                                                                                                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------------+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                         ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                              ; Clock Edge ; Target                                                                                                   ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.601 ; 17.601       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.616 ; 17.616       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.619 ; 17.619       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.623 ; 17.623       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.626 ; 17.626       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]                      ;
; 17.640 ; 17.640       ; 0.000          ; High Pulse Width ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+------------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                              ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                       ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+
; 89.498  ; 99.598       ; 10.100         ; High Pulse Width ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 90.297  ; 100.397      ; 10.100         ; Low Pulse Width  ; FPGA_CLK ; Fall       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|wire_sd4_regout        ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[0]              ;
; 99.265  ; 99.449       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[1]              ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 99.266  ; 99.450       ; 0.184          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|synchronizer:reboot_synchronizer|ff_reg[2]              ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                          ;
; 99.407  ; 99.407       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|observablevcoout                                ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                             ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[0]|clk                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[1]|clk                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reboot_synchronizer|ff_reg[2]|clk                                        ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[0]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[10]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[11]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[12]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[13]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[14]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[15]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[16]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[17]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[18]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[19]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[1]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[20]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[21]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[22]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[23]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[24]|clk                                               ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[2]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[3]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[4]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[5]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[6]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[7]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[8]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|reconfig_count_reg[9]|clk                                                ;
; 99.444  ; 99.444       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|dffe8|clk                                                         ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 99.452  ; 99.452       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|inclk[0]                                        ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|inclk[0]                                                               ;
; 99.453  ; 99.453       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~inputclkctrl|outclk                                                                 ;
; 99.548  ; 99.548       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|rublock_clock|combout                                             ;
; 99.553  ; 99.553       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; return_to_boot_menu|remote|rublock_clock|datad                                               ;
; 99.598  ; 99.598       ; 0.000          ; High Pulse Width ; FPGA_CLK ; Fall       ; return_to_boot_menu|remote|sd4|clk                                                           ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                             ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[0]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[10]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[11]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[12]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[13]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[14]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[15]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[16]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[17]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[18]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[19]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[1]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[20]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[21]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[22]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[23]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[24]                                  ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[2]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[3]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[4]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[5]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[6]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[7]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[8]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|reconfig_count_reg[9]                                   ;
; 100.334 ; 100.550      ; 0.216          ; High Pulse Width ; FPGA_CLK ; Rise       ; delayed_reconfig:return_to_boot_menu|remote_update_rmtupdt_51n:remote|dffe8                  ;
+---------+--------------+----------------+------------------+----------+------------+----------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.534 ; 2.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.500 ; 2.058 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.500 ; 2.058 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.500 ; 2.058 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.513 ; 2.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.522 ; 2.080 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.519 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.514 ; 2.072 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.523 ; 2.081 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.528 ; 2.086 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.534 ; 2.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.530 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.530 ; 2.088 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.520 ; 2.078 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.519 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.509 ; 2.067 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.519 ; 2.077 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 3.985 ; 4.453 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.263 ; 2.738 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 1.961 ; 2.493 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.255 ; 2.793 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.249 ; 2.781 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.985 ; 4.453 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 3.648 ; 4.003 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 2.318 ; 2.774 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.230 ; 2.729 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.790 ; 3.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.799 ; 3.328 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.648 ; 4.003 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.063 ; 3.822 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 2.806 ; 3.531 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 2.046 ; 2.535 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.437 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.058 ; -1.616 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.050 ; -1.608 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.059 ; -1.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.064 ; -1.622 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.070 ; -1.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.056 ; -1.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.045 ; -1.603 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.459 ; -1.973 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.753 ; -2.225 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.459 ; -1.973 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.718 ; -2.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.713 ; -2.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.036 ; -2.580 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.715 ; -2.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.799 ; -2.249 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.715 ; -2.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.233 ; -2.750 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.241 ; -2.744 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.746 ; -2.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.518 ; -3.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.271 ; -2.984 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.546 ; -2.031 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.108 ; -0.668 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.546 ; 2.252 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.577 ; 1.426 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.567 ; 1.416 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.553 ; 1.402 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.561 ; 1.410 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.571 ; 1.420 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.546 ; 2.252 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.572 ; 1.421 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.582 ; 1.431 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.578 ; 1.427 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.553 ; 2.259 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.579 ; 1.428 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.553 ; 2.259 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.565 ; 2.271 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.589 ; 1.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.598 ; 2.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.598 ; 2.320 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.589 ; 2.311 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.131 ; 1.043 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.654 ; 1.504 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.665 ; 1.515 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.737 ; 1.591 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.597 ; 2.319 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.735 ; 1.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.735 ; 1.589 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.725 ; 1.579 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.592 ; 2.314 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.716 ; 1.570 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.726 ; 1.580 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.716 ; 1.701 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.630 ; 1.609 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.716 ; 1.701 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.589 ; 1.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.600 ; 1.449 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 4.015 ; 4.675 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.948 ; 2.065 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.051 ; 2.217 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.939 ; 4.572 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.777 ; 1.692 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.027 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.972 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 2.877 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.257 ; 1.276 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.875 ; 3.343 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.091 ; 1.153 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.877 ; 3.345 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 2.833 ; 3.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.833 ; 3.266 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.056 ; 1.022 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.066 ; 1.032 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.056 ; 1.022 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.822 ; 3.255 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.047 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.035 ; 1.001 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.045 ; 1.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.047 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.037 ; 1.003 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 1.045 ; 1.011 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.927 ; 1.893 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.146 ; 0.997 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.155 ; 1.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.152 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.156 ; 1.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.166 ; 1.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.162 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.159 ; 1.865 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.170 ; 1.876 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.738 ; 0.650 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.205 ; 1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.196 ; 1.918 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.738 ; 0.650 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.237 ; 1.089 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.248 ; 1.100 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.320 ; 1.176 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.204 ; 1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.199 ; 1.921 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.299 ; 1.155 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.309 ; 1.165 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.213 ; 1.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.213 ; 1.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.296 ; 1.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.183 ; 1.034 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.581 ; 4.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.532 ; 1.645 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.622 ; 1.780 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.504 ; 4.130 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.358 ; 1.276 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.658 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.601 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.698 ; 0.760 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.865 ; 0.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.482 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.698 ; 0.760 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.484 ; 2.952 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.439 ; 2.872 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.673 ; 0.639 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.428 ; 2.861 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.651 ; 0.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.653 ; 0.619 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.643 ; 0.609 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.652 ; 0.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                           ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.883 ; 1.856 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.227 ; 2.200 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.227 ; 2.200 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.227 ; 2.200 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.421 ; 2.394 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.590 ; 2.563 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.753 ; 2.726 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.790 ; 2.763 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.786 ; 2.759 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.237 ; 2.210 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.072 ; 2.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.893 ; 1.866 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.893 ; 1.866 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.883 ; 1.856 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.034 ; 2.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.024 ; 1.997 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.034 ; 2.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.077 ; 2.701 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.976 ; 3.600 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.976 ; 3.600 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.595 ; 0.595 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.924 ; 0.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.924 ; 0.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.924 ; 0.924 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.111 ; 1.111 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.273 ; 1.273 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.429 ; 1.429 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.465 ; 1.465 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.462 ; 1.462 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 0.934 ; 0.934 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 0.776 ; 0.776 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.605 ; 0.605 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.605 ; 0.605 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.595 ; 0.595 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.739 ; 0.739 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.729 ; 0.729 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.739 ; 0.739 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.553 ; 2.192 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.588 ; 3.227 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.588 ; 3.227 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                                  ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.927     ; 1.927     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.297     ; 2.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.297     ; 2.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.297     ; 2.297     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.510     ; 2.510     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.697     ; 2.697     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.880     ; 2.880     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.911     ; 2.911     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.908     ; 2.908     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.303     ; 2.303     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.123     ; 2.123     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.937     ; 1.937     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.937     ; 1.937     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.927     ; 1.927     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.096     ; 2.096     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.086     ; 2.086     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.096     ; 2.096     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.873     ; 3.249     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.735     ; 4.111     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.735     ; 4.111     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                          ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.636     ; 0.753     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.991     ; 1.108     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.991     ; 1.108     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.991     ; 1.108     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.196     ; 1.313     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.376     ; 1.493     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.551     ; 1.668     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.581     ; 1.698     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.579     ; 1.696     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 0.998     ; 1.115     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 0.825     ; 0.942     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 0.646     ; 0.763     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 0.646     ; 0.763     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 0.636     ; 0.753     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 0.798     ; 0.915     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 0.788     ; 0.905     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 0.798     ; 0.915     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.357     ; 2.718     ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 3.356     ; 3.717     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 3.356     ; 3.717     ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-----------+-----------+------------+-------------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                                  ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Clock                                                                                ; Setup    ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+
; Worst-case Slack                                                                     ; -4.101   ; -1.121  ; -2.487   ; -0.486  ; 5.570               ;
;  FPGA_CLK                                                                            ; -0.437   ; -0.721  ; -0.568   ; -0.486  ; 89.483              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.506    ; 0.187   ; 7.304    ; 1.227   ; 5.570               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -4.101   ; 0.154   ; 7.411    ; 1.043   ; 17.187              ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.117   ; 11.450  ; N/A      ; N/A     ; 5.696               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 4.880    ; 0.151   ; 12.484   ; 1.465   ; 8.507               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 17.589              ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -1.248   ; -1.121  ; -2.487   ; -0.056  ; 9.345               ;
; Design-wide TNS                                                                      ; -199.723 ; -42.083 ; -35.361  ; -12.695 ; 0.0                 ;
;  FPGA_CLK                                                                            ; -0.437   ; -0.721  ; -14.742  ; -12.373 ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; -158.000 ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; -2.117   ; 0.000   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 0.000    ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A      ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; -41.748  ; -41.362 ; -22.359  ; -0.496  ; 0.000               ;
+--------------------------------------------------------------------------------------+----------+---------+----------+---------+---------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                                   ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.134 ; 3.241 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.096 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.107 ; 3.214 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.116 ; 3.223 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.114 ; 3.221 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.108 ; 3.215 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.117 ; 3.224 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.134 ; 3.241 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.130 ; 3.237 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.120 ; 3.227 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.119 ; 3.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.109 ; 3.216 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.119 ; 3.226 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 8.430 ; 8.834 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.568 ; 4.836 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.049 ; 4.321 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.755 ; 5.028 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.737 ; 4.977 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 8.430 ; 8.834 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 7.433 ; 7.901 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 4.613 ; 4.831 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.554 ; 4.863 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 5.900 ; 6.015 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 5.927 ; 6.042 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 7.433 ; 7.901 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.322 ; 6.584 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.744 ; 6.068 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 4.140 ; 4.296 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; 0.864 ; 0.997 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                      ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                     ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.036 ; -1.594 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.049 ; -1.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.058 ; -1.616 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.050 ; -1.608 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.059 ; -1.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.064 ; -1.622 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.070 ; -1.628 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.066 ; -1.624 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.056 ; -1.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.045 ; -1.603 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.055 ; -1.613 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.459 ; -1.973 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.753 ; -2.225 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.459 ; -1.973 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.718 ; -2.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.713 ; -2.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.036 ; -2.580 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.715 ; -2.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.799 ; -2.249 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.715 ; -2.205 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -2.233 ; -2.750 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -2.241 ; -2.744 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.746 ; -2.218 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.518 ; -3.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.271 ; -2.984 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.546 ; -2.031 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; USB2_N        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P        ; FPGA_CLK   ; -0.093 ; -0.204 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+---------------+------------+--------+--------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                           ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.244 ; 3.008 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.223 ; 2.987 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.231 ; 2.995 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.240 ; 3.004 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.495 ; 4.045 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.242 ; 3.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.252 ; 3.016 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.254 ; 3.018 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.255 ; 3.019 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.509 ; 4.059 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.521 ; 4.071 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.538 ; 3.281 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.568 ; 4.120 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.559 ; 4.111 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.490 ; 2.292 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.435 ; 3.192 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.446 ; 3.203 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.545 ; 3.288 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.562 ; 4.114 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.542 ; 3.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.542 ; 3.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.532 ; 3.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.558 ; 4.110 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.524 ; 3.267 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.534 ; 3.277 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 3.510 ; 3.857 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.349 ; 3.647 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.510 ; 3.857 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.265 ; 3.029 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.276 ; 3.040 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 7.991 ; 8.021 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.358 ; 4.092 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.803 ; 4.438 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.708 ; 7.812 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.632 ; 3.832 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.997 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.719 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.273 ; 5.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 2.693 ; 2.663 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.266 ; 5.614 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 2.491 ; 2.441 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.273 ; 5.621 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.162 ; 5.455 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 2.402 ; 2.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 2.412 ; 2.295 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 2.402 ; 2.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 5.151 ; 5.444 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 2.380 ; 2.263 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 2.390 ; 2.273 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 2.392 ; 2.275 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 2.382 ; 2.265 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 2.391 ; 2.274 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 4.032 ; 3.908 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                                   ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                     ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.161 ; 1.012 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.151 ; 1.002 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.137 ; 0.988 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.146 ; 0.997 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.155 ; 1.006 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.152 ; 1.858 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.156 ; 1.007 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.166 ; 1.017 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.162 ; 1.013 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.163 ; 1.014 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.159 ; 1.865 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.170 ; 1.876 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.738 ; 0.650 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.205 ; 1.927 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.196 ; 1.918 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.738 ; 0.650 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.237 ; 1.089 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.248 ; 1.100 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.320 ; 1.176 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.204 ; 1.926 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.318 ; 1.174 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.308 ; 1.164 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.199 ; 1.921 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.299 ; 1.155 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.309 ; 1.165 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.213 ; 1.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 1.213 ; 1.196 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.296 ; 1.285 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.173 ; 1.024 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.183 ; 1.034 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.581 ; 4.234 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.532 ; 1.645 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.622 ; 1.780 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.504 ; 4.130 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.358 ; 1.276 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.658 ;       ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.601 ; Fall       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; VGA_B[*]        ; FPGA_CLK   ; 0.698 ; 0.760 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[0]       ; FPGA_CLK   ; 0.865 ; 0.884 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[1]       ; FPGA_CLK   ; 2.482 ; 2.950 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[2]       ; FPGA_CLK   ; 0.698 ; 0.760 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_B[3]       ; FPGA_CLK   ; 2.484 ; 2.952 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_G[*]        ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[0]       ; FPGA_CLK   ; 2.439 ; 2.872 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[1]       ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[2]       ; FPGA_CLK   ; 0.673 ; 0.639 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_G[3]       ; FPGA_CLK   ; 0.663 ; 0.629 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_HS          ; FPGA_CLK   ; 2.428 ; 2.861 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_R[*]        ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[0]       ; FPGA_CLK   ; 0.641 ; 0.607 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[1]       ; FPGA_CLK   ; 0.651 ; 0.617 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[2]       ; FPGA_CLK   ; 0.653 ; 0.619 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
;  VGA_R[3]       ; FPGA_CLK   ; 0.643 ; 0.609 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; VGA_VS          ; FPGA_CLK   ; 0.652 ; 0.618 ; Rise       ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ;
; USB2_N          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
; USB2_P          ; FPGA_CLK   ; 1.669 ; 1.635 ; Rise       ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ;
+-----------------+------------+-------+-------+------------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_P         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; USB2_N         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; USB2_P       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; USB2_N       ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; USB2_P         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; USB2_N         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                                       ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10323    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 12539766 ; 0        ; 109296   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 47       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 315      ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1656     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 41       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 12212    ; 7        ; 43       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                                        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1826     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1        ; 248      ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 10323    ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 12539766 ; 0        ; 109296   ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 47       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] ; 0        ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 315      ; 0        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 1656     ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 1        ; 0        ; 0        ; 0        ;
; FPGA_CLK                                                                            ; FPGA_CLK                                                                            ; 352      ; 1        ; 1        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 41       ; 0        ; 0        ; 0        ;
; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 12212    ; 7        ; 43       ; 1        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                                    ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 677      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5145     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 176      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                                     ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                          ; To Clock                                                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 677      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5145     ; 0        ; 59       ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] ; 176      ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; FPGA_CLK                                                                            ; 26       ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
; \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] ; usb_pll|altpll_component|auto_generated|pll1|clk[0]                                 ; 9        ; 0        ; 0        ; 0        ;
+-------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 31    ; 31   ;
; Unconstrained Input Port Paths  ; 63    ; 63   ;
; Unconstrained Output Ports      ; 57    ; 57   ;
; Unconstrained Output Port Paths ; 77    ; 77   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sat Jul 13 22:16:58 2019
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 12 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 6 of the 6 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 225.00 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 2 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]} {\gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4]}
    Info (332110): create_generated_clock -source {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 40 -multiply_by 227 -duty_cycle 50.00 -name {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {usb_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 48 -duty_cycle 50.00 -name {usb_pll|altpll_component|auto_generated|pll1|clk[0]} {usb_pll|altpll_component|auto_generated|pll1|clk[0]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] could not be matched with a clock
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] could not be matched with a clock
Warning (332174): Ignored filter at atari800core.sdc(5): \gen_real_pll:gen_tv_pal:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] could not be matched with a clock
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -4.101
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -4.101      -158.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -2.117        -2.117 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -1.199       -39.377 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.229        -0.229 FPGA_CLK 
    Info (332119):     0.506         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.880         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -1.121
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.121       -41.362 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.721        -0.721 FPGA_CLK 
    Info (332119):     0.435         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.455         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.455         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.965         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.487
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.487       -22.359 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.458       -11.870 FPGA_CLK 
    Info (332119):     7.304         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.411         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    12.484         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.486
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.486       -12.373 FPGA_CLK 
    Info (332119):     0.264         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.343         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.870         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.386         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.570
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.570         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.696         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.507         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.346         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.589         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.483         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -3.721
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -3.721      -140.347 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -1.812        -1.812 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    -1.248       -41.748 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.437        -0.437 FPGA_CLK 
    Info (332119):     0.774         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.199         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -0.985
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.985       -35.916 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.511        -0.511 FPGA_CLK 
    Info (332119):     0.386         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.404         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.404         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):    12.680         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -2.291
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.291       -20.619 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.568       -14.742 FPGA_CLK 
    Info (332119):     7.677         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.808         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    12.845         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.336
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.336        -8.436 FPGA_CLK 
    Info (332119):     0.273         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.088         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.554         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.004         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.571
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.571         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.716         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.509         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.345         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.220         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.590         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.536         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
    Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Info (332146): Worst-case setup slack is -1.924
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.924       -75.818 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    -0.584       -18.506 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.191        -0.191 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.301         0.000 FPGA_CLK 
    Info (332119):     3.494         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.025         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case hold slack is -0.684
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.684       -26.206 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    -0.586        -0.586 FPGA_CLK 
    Info (332119):     0.151         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     0.154         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.187         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    11.450         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
Info (332146): Worst-case recovery slack is -1.139
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.139       -10.243 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.294         0.000 FPGA_CLK 
    Info (332119):     9.635         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     9.754         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    15.227         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case removal slack is -0.474
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -0.474       -12.199 FPGA_CLK 
    Info (332119):    -0.056        -0.496 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.043         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.227         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     1.465         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
Info (332146): Worst-case minimum pulse width slack is 5.655
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.655         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     5.801         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     8.561         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[4] 
    Info (332119):     9.381         0.000 usb_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.369         0.000 \gen_real_pll:pll_switcher|generic_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.601         0.000 \gen_real_pll:pll_switcher|generic_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    89.498         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 578 megabytes
    Info: Processing ended: Sat Jul 13 22:17:07 2019
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:13


